testcoreb.map.xml

OV7660驱动程序

<?xml version="1.0" standalone="no"?>
<?xml-stylesheet type="text/xsl" href="file:///D:/Program Files/Analog Devices/VisualDSP 4.5/System/linker_map_ss1.xsl"?>
<!DOCTYPE DOCUMENT SYSTEM "file:///D:/Program Files/Analog Devices/VisualDSP 4.5/System/linker_map.dtd">
<DOCUMENT>
<LINKPROJECT guid='d2825cd73be786e15' id='021429C0' name='p1' orig_file_name='Debug\testcoreb.dxe' architecture='ADSP-BF561' >
<FILE_NAME><![CDATA[Debug\testcoreb.dxe]]></FILE_NAME>
<MEMORY id='00E1E238' name='MEM_L2_SRAM' start_address='0xfeb00000' end_address='0xfeb0efff' type='' qualifier='RAM' width='0x8' words_used='0x0' words_unused='0xf000' >
<OUTPUT_SECTIONS>
</OUTPUT_SECTIONS>
</MEMORY>
<MEMORY id='00E1ED10' name='MEM_ASYNC3' start_address='0x2c000000' end_address='0x2fffffff' type='' qualifier='RAM' width='0x8' words_used='0x0' words_unused='0x4000000' >
<OUTPUT_SECTIONS>
</OUTPUT_SECTIONS>
</MEMORY>
<MEMORY id='00E1EC88' name='MEM_ASYNC2' start_address='0x28000000' end_address='0x2bffffff' type='' qualifier='RAM' width='0x8' words_used='0x0' words_unused='0x4000000' >
<OUTPUT_SECTIONS>
</OUTPUT_SECTIONS>
</MEMORY>
<MEMORY id='00E1EB78' name='MEM_ASYNC1' start_address='0x24000000' end_address='0x27ffffff' type='' qualifier='RAM' width='0x8' words_used='0x0' words_unused='0x4000000' >
<OUTPUT_SECTIONS>
</OUTPUT_SECTIONS>
</MEMORY>
<MEMORY id='00E1E8B0' name='MEM_ASYNC0' start_address='0x20000000' end_address='0x23ffffff' type='' qualifier='RAM' width='0x8' words_used='0x0' words_unused='0x4000000' >
<OUTPUT_SECTIONS>
</OUTPUT_SECTIONS>
</MEMORY>
<MEMORY id='00E1F1B0' name='MEM_SDRAM_BANK0' start_address='0x2000000' end_address='0x27fffff' type='' qualifier='RAM' width='0x8' words_used='0x0' words_unused='0x800000' >
<OUTPUT_SECTIONS>
<OUTPUT_SECTION name='sdram_bank0' id='029CD0F0' memory_id='00E1F1B0' type='SHT_PROGBITS' start_address='0x2000000' word_size='0x0' word_size_unmapped='0x0' word_size_reserved='0x0' >
<INPUT_SECTIONS>
</INPUT_SECTIONS>
</OUTPUT_SECTION>
</OUTPUT_SECTIONS>
</MEMORY>
<MEMORY id='00E29598' name='MEM_SDRAM_BANK1' start_address='0x2800000' end_address='0x2ffffff' type='' qualifier='RAM' width='0x8' words_used='0x0' words_unused='0x800000' >
<OUTPUT_SECTIONS>
<OUTPUT_SECTION name='sdram_bank1' id='029D5AF0' memory_id='00E29598' type='SHT_PROGBITS' start_address='0x2800000' word_size='0x0' word_size_unmapped='0x0' word_size_reserved='0x0' >
<INPUT_SECTIONS>
</INPUT_SECTIONS>
</OUTPUT_SECTION>
</OUTPUT_SECTIONS>
</MEMORY>
<MEMORY id='00ECC320' name='MEM_SDRAM_BANK2' start_address='0x3000000' end_address='0x37fffff' type='' qualifier='RAM' width='0x8' words_used='0x0' words_unused='0x800000' >
<OUTPUT_SECTIONS>
<OUTPUT_SECTION name='sdram_bank2' id='029B23B8' memory_id='00ECC320' type='SHT_PROGBITS' start_address='0x3000000' word_size='0x0' word_size_unmapped='0x0' word_size_reserved='0x0' >
<INPUT_SECTIONS>
</INPUT_SECTIONS>
</OUTPUT_SECTION>
</OUTPUT_SECTIONS>
</MEMORY>
<MEMORY id='020EDCC8' name='MEM_SDRAM_BANK3' start_address='0x3800000' end_address='0x3ffffff' type='' qualifier='RAM' width='0x8' words_used='0x0' words_unused='0x800000' >
<OUTPUT_SECTIONS>
<OUTPUT_SECTION name='sdram_bank3' id='029A6198' memory_id='020EDCC8' type='SHT_PROGBITS' start_address='0x3800000' word_size='0x0' word_size_unmapped='0x0' word_size_reserved='0x0' >
<INPUT_SECTIONS>
</INPUT_SECTIONS>
</OUTPUT_SECTION>
<OUTPUT_SECTION name='sdram_bank3_1' id='029A64E0' memory_id='020EDCC8' type='SHT_PROGBITS' start_address='0x3800000' word_size='0x0' word_size_unmapped='0x0' word_size_reserved='0x0' >
<INPUT_SECTIONS>
</INPUT_SECTIONS>
</OUTPUT_SECTION>
<OUTPUT_SECTION name='sdram_bank3_bsz' id='029A6B40' memory_id='020EDCC8' type='SHT_NOBITS' start_address='0x3800000' word_size='0x0' word_size_unmapped='0x0' word_size_reserved='0x0' >
<INPUT_SECTIONS>
</INPUT_SECTIONS>
</OUTPUT_SECTION>
<OUTPUT_SECTION name='sdram_bank3_2' id='029CB6B8' memory_id='020EDCC8' type='SHT_PROGBITS' start_address='0x3800000' word_size='0x0' word_size_unmapped='0x0' word_size_reserved='0x0' >
<INPUT_SECTIONS>
</INPUT_SECTIONS>
</OUTPUT_SECTION>
<OUTPUT_SECTION name='sdram_bank3_3' id='029A05E0' memory_id='020EDCC8' type='SHT_PROGBITS' start_address='0x3800000' word_size='0x0' word_size_unmapped='0x0' word_size_reserved='0x0' >
<INPUT_SECTIONS>
</INPUT_SECTIONS>
</OUTPUT_SECTION>
</OUTPUT_SECTIONS>
</MEMORY>
<MEMORY id='020FD828' name='MEM_L2_SRAM_SHARED' start_address='0xfeb0f000' end_address='0xfeb0ffff' type='' qualifier='RAM' width='0x8' words_used='0x0' words_unused='0x1000' >
<OUTPUT_SECTIONS>
<OUTPUT_SECTION name='shared_l2' id='029BEF90' memory_id='020FD828' type='SHT_NOBITS' start_address='0xfeb0f000' word_size='0x0' word_size_unmapped='0x0' word_size_reserved='0x0' >
<INPUT_SECTIONS>
</INPUT_SECTIONS>
</OUTPUT_SECTION>
</OUTPUT_SECTIONS>
</MEMORY>
<MEMORY id='020FD778' name='MEM_L2_SRAM_B' start_address='0xfeb10000' end_address='0xfeb17fff' type='' qualifier='RAM' width='0x8' words_used='0x0' words_unused='0x8000' >
<OUTPUT_SECTIONS>
<OUTPUT_SECTION name='L2_sram_b' id='029B93C8' memory_id='020FD778' type='SHT_PROGBITS' start_address='0xfeb10000' word_size='0x0' word_size_unmapped='0x0' word_size_reserved='0x0' >
<INPUT_SECTIONS>
</INPUT_SECTIONS>
</OUTPUT_SECTION>
<OUTPUT_SECTION name='bsz_L2_sram_b' id='029CCF60' memory_id='020FD778' type='SHT_NOBITS' start_address='0xfeb10000' word_size='0x0' word_size_unmapped='0x0' word_size_reserved='0x0' >
<INPUT_SECTIONS>
</INPUT_SECTIONS>
</OUTPUT_SECTION>
<OUTPUT_SECTION name='L2_sram_b_stack_heap' id='029C0160' memory_id='020FD778' type='SHT_PROGBITS' start_address='0xfeb10000' word_size='0x0' word_size_unmapped='0x0' word_size_reserved='0x0' >
<INPUT_SECTIONS>
</INPUT_SECTIONS>
</OUTPUT_SECTION>
</OUTPUT_SECTIONS>
</MEMORY>
<MEMORY id='020FBDA0' name='MEM_B_L1_SCRATCH' start_address='0xff700000' end_address='0xff700fff' type='' qualifier='RAM' width='0x8' words_used='0x0' words_unused='0x1000' >
<OUTPUT_SECTIONS>
<OUTPUT_SECTION name='scratchpad' id='029A5FC0' memory_id='020FBDA0' type='SHT_PROGBITS' start_address='0xff700000' word_size='0x0' word_size_unmapped='0x0' word_size_reserved='0x0' >
<INPUT_SECTIONS>
</INPUT_SECTIONS>
</OUTPUT_SECTION>
</OUTPUT_SECTIONS>
</MEMORY>
<MEMORY id='020F7BB8' name='MEM_B_L1_CODE_CACHE' start_address='0xff610000' end_address='0xff613fff' type='' qualifier='RAM' width='0x8' words_used='0x0' words_unused='0x4000' >
<OUTPUT_SECTIONS>
<OUTPUT_SECTION name='L1_code_cache' id='0299EED8' memory_id='020F7BB8' type='SHT_PROGBITS' start_address='0xff610000' word_size='0x0' word_size_unmapped='0x0' word_size_reserved='0x0' >
<INPUT_SECTIONS>
</INPUT_SECTIONS>
</OUTPUT_SECTION>
</OUTPUT_SECTIONS>
</MEMORY>
<MEMORY id='020E3640' name='MEM_B_L1_CODE' start_address='0xff600000' end_address='0xff603fff' type='' qualifier='RAM' width='0x8' words_used='0x31ae' words_unused='0xe52' >
<OUTPUT_SECTIONS>
<OUTPUT_SECTION name='L1_code' id='028E42F8' memory_id='020E3640' type='SHT_PROGBITS' start_address='0xff600000' word_size='0x31ae' word_size_unmapped='0x0' word_size_reserved='0x0' >
<INPUT_SECTIONS>
<INPUT_SECTION id='0291B458' name='cplb_code' start_address='0xff6000e4' size='0xc6' element_at='0x0' >
<INPUT_FILE><![CDATA[libevent561y.dlb[cplbhdr.doj]]]></INPUT_FILE>
<SYMBOL name='_cplb_hdr' address='0xff6000e4' size='0xc6' binding='GLOBAL'><DEMANGLED_NAME><![CDATA[cplb_hdr]]></DEMANGLED_NAME></SYMBOL>
<SYMBOL name='.wa05000283' address='0xff6000f6' size='0x0' binding='LOCAL'><DEMANGLED_NAME><![CDATA[]]></DEMANGLED_NAME></SYMBOL>