corea.c

OV7660驱动程序

#include "corea.h"
#include "cache.h"

						
 
int *corea_coreb_exchange_flag=(int *)COREA_COREB_EXCHANGE_FLAG;
	
sFrameAddr_buffer	*sFrameAddr=(sFrameAddr_buffer *)SHARE_SDRAM_BASE_ADDR ;
	  
//--------------------------------------------------------------------------//
// Function:	Init_Interrupts												//
//																			//
// Description:	Initialize Interrupt for PPI0 RX							//
//--------------------------------------------------------------------------//

void Init_PPI0_Interrupts(void)
{
	// assign interrupt channel 11 (DMA1_0) to IVG8 
	*pSICB_IAR1 = Peripheral_IVG(11,8);	
	
	// assign ISRs to interrupt vectors
	// PPI0 RX ISR -> IVG 8
	register_handler(ik_ivg8, PPI0_RX_ISR);		

	// clear pending IVG8 interrupts
	*pILAT |= EVT_IVG8;		
	ssync();
	
	// enable Sport0 RX interrupt
	*pSICB_IMASK0 |= SIC_MASK(11);
	ssync();
	
}

//--------------------------------------------------------------------------//
// Function:	PPI0_RX_ISR												//
//																			//
// Description: This ISR is executed after a complete frame of input data 	//
//				has been received. The new samples are stored in 			//
//				iChannel0LeftIn, iChannel0RightIn, iChannel1LeftIn and 		//
//				iChannel1RightIn respectively.  Then the function 			//
//				Process_Data() is called in which user code can be executed.//
//				After that the processed values are copied from the 		//
//				variables iChannel0LeftOut, iChannel0RightOut, 				//
//				iChannel1LeftOut and iChannel1RightOut into the dma 		//
//				transmit buffer.											//
//--------------------------------------------------------------------------//
EX_INTERRUPT_HANDLER(PPI0_RX_ISR)
{
	// confirm interrupt handling

	*pDMA1_0_IRQ_STATUS = 0x0001;
	
	
	DCacheInv((void*)corea_coreb_exchange_flag, sizeof(*corea_coreb_exchange_flag));	
   
	*corea_coreb_exchange_flag=COREB_DMA_STOP;
    
	DCacheFlush((void*)corea_coreb_exchange_flag, sizeof(*corea_coreb_exchange_flag));
		   


}

		
void setup_dma(void) {
	*pDMA1_0_START_ADDR = (volatile int) sFrameAddr;
	ssync();
	*pDMA1_0_X_COUNT = PIXEL_PER_LINE;
	ssync();
	*pDMA1_0_Y_COUNT = LINES_PER_FRAME;
	ssync();
	*pDMA1_0_X_MODIFY = 2;
	ssync();
	*pDMA1_0_Y_MODIFY = 2;
	ssync();	
	*pDMA1_0_CONFIG = DMA_FLOW_MODE | RESTART | DI_EN | DMA2D | DMA_16BITS | WNR;
	ssync();	
}

void enable_dma(void) {
	*pDMA1_0_CONFIG |= DMAEN;
	ssync();
}

void setup_ppi(void) {
	*pPPI0_FRAME = LINES_PER_FRAME;
	ssync();
	*pPPI0_COUNT = PIXEL_PER_LINE*2 - 1;
	ssync();
	*pPPI0_CONTROL = POL_C | POL_S | DATALEN | PACK_EN | CFG_GP_INPUT_3SYNCS | GP_INPUT_MODE;

	//*pPPI0_CONTROL = DATALEN | PACK_EN;
	ssync();
}

void enable_ppi(void) {
	*pPPI0_CONTROL |= PORT_EN;
	ssync();
}

void disable_dma(void) {
	while (!(*pDMA1_0_IRQ_STATUS &= DMA_DONE))
		ssync();
	*pDMA1_0_IRQ_STATUS |= DMA_DONE;
	ssync();
	*pPPI0_CONTROL = ~PORT_EN;
	ssync();
	*pDMA1_0_CONFIG &= ~DMAEN;
	ssync();
}

main() {
	
	unsigned int i;
	
	*corea_coreb_exchange_flag=0;
	
  //  corea_coreb_exchange_flag=(int *)COREA_COREB_EXCHANGE_FLAG;
	
  // 	sFrameAddr=(sFrameAddr_buffer *)SHARE_SDRAM_BASE_ADDR ;
	  
    Init_PPI0_Interrupts();

	for (i = 0; i < 20; i++) {
			
		setup_dma();
		enable_dma();
	
		setup_ppi();
		enable_ppi();
	
		disable_dma();
	
		
		ssync();
		ssync();
	}
	#if 0
     	DCacheInv((void*)corea_coreb_exchange_flag, sizeof(*corea_coreb_exchange_flag));	
    	*corea_coreb_exchange_flag=10;
    	DCacheFlush((void*)corea_coreb_exchange_flag, sizeof(*corea_coreb_exchange_flag));	
    
	#endif

	while (1) {
		
		
		switch(*corea_coreb_exchange_flag){
			
		     
		   case COREB_DMA_START:
		   
		     {
            	setup_dma();
	            enable_dma();
	
	            setup_ppi();
	            enable_ppi();	
	            
	            ssync();
		        
	            
	            break;	   	
		     }
		   
		   case COREB_DMA_STOP:
		
		    	disable_dma();
		    	
           default: 
                
                break;   
		}
		
		ssync();
	}

}