initialize.c

WM8731的驱动程序

#include "Talkthrough.h"


void Initwm8731(void)
{
	wm8731_init();
}






void Init_Sport0(void)
{
	// Sport0 receive configuration
	// External CLK, External Frame sync, MSB first, Active Low
	// 24-bit data, Stereo frame sync enable
	*pSPORT0_RCR1 = RFSR | RCKFE ;// LARFS |
	*pSPORT0_RCR2 = SLEN_24 |  RSFSE; //RXSE |
	
	// Sport0 transmit configuration
	// External CLK, External Frame sync, MSB first, Active Low
	// 24-bit data, Secondary side enable, Stereo frame sync enable
	*pSPORT0_TCR1 = TFSR | TCKFE;  //  LATFS |
	*pSPORT0_TCR2 = SLEN_24 |  TSFSE;  //TXSE |
  
	
/*	// Enable MCM 8 transmit & receive channels
	*pSPORT0_MTCS0 = 0x00000003;
	*pSPORT0_MRCS0 = 0x00000003;
	
	// Set MCM configuration register and enable MCM mode
	*pSPORT0_MCMC1 = 0x0000;
	*pSPORT0_MCMC2 = 0x101c;
*/

}


//--------------------------------------------------------------------------//
// Function:	Init_DMA													//
//																			//
// Description:	Initialize DMA2_0 in autobuffer mode to receive and DMA2_1 	//
//				in autobuffer mode to transmit								//
//--------------------------------------------------------------------------//
void Init_DMA(void)
{
	// Set up DMA2 channel 0 to Sport receive
	*pDMA2_0_PERIPHERAL_MAP =  0x0000;

	// Configure DMA2 channel0
	// 32-bit transfers, Interrupt on completion, Autobuffer mode
	*pDMA2_0_CONFIG = WNR | WDSIZE_32 | DI_EN | FLOW_1 ;
 //    *pDMA2_0_CONFIG = WNR | WDSIZE_32 | FLOW_1;
	// Start address of data buffer
	*pDMA2_0_START_ADDR =(volatile int)iRxBuffer1;
	// DMA inner loop count
	*pDMA2_0_X_COUNT = 2;
	// Inner loop address increment
	*pDMA2_0_X_MODIFY	= 4;
	
	
	// Set up DMA2 channel 1 to Sport transmit
	*pDMA2_1_PERIPHERAL_MAP = 0x1000;
	
	// Configure DMA2 channel 1
	// 32-bit transfers, Autobuffer mode
	*pDMA2_1_CONFIG = WDSIZE_32 | FLOW_1|DI_EN;
	// Start address of data buffer
	*pDMA2_1_START_ADDR = (volatile int)iTxBuffer1;
	// DMA inner loop count
	*pDMA2_1_X_COUNT = 2;
	// Inner loop address increment
	*pDMA2_1_X_MODIFY	= 4;
}


//--------------------------------------------------------------------------//
// Function:	Init_Interrupts												//
//																			//
// Description:	Initialize Interrupt for Sport0 RX							//
//--------------------------------------------------------------------------//

void Init_Sport_Interrupts(void)
{
	// assign interrupt channel 23 (DMA2_0) to IVG9 
	*pSICA_IAR2 = Peripheral_IVG(23,9);	
	
	// assign ISRs to interrupt vectors
	// Sport0 RX ISR -> IVG 9
	register_handler(ik_ivg9, Sport0_RX_ISR);		

	// clear pending IVG9 interrupts
	*pILAT |= EVT_IVG9;		
	ssync();
	
	// enable Sport0 RX interrupt
	*pSICA_IMASK0 |= SIC_MASK(23);
	ssync();
	
}


//--------------------------------------------------------------------------//
// Function:	Enable_DMA_Sport											//
//																			//
// Description:	Enable DMA2_0, DMA2_1, Sport0 TX and Sport0 RX					//
//--------------------------------------------------------------------------//
void Enable_DMA_Sport0(void)
{
	// enable DMAs
	*pDMA2_1_CONFIG	= (*pDMA2_1_CONFIG | DMAEN);
	*pDMA2_0_CONFIG	= (*pDMA2_0_CONFIG | DMAEN);
	
	// enable Sport0 TX and RX
	*pSPORT0_TCR1 	= (*pSPORT0_TCR1 | TSPEN);
	*pSPORT0_RCR1 	= (*pSPORT0_RCR1 | RSPEN);
	
}



void Disable_DMA_Sport0(void)
{
	// enable DMAs
	*pDMA2_1_CONFIG	= (*pDMA2_1_CONFIG & 0xfe);
	*pDMA2_0_CONFIG	= (*pDMA2_0_CONFIG & 0xfe);
	
	// enable Sport0 TX and RX
	*pSPORT0_TCR1 	= (*pSPORT0_TCR1 & 0xfe);
	*pSPORT0_RCR1 	= (*pSPORT0_RCR1 & 0xfe);
}