📄 main.lst
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C51 COMPILER V8.12 MAIN 04/03/2009 01:00:38 PAGE 1
C51 COMPILER V8.12, COMPILATION OF MODULE MAIN
OBJECT MODULE PLACED IN main.obj
COMPILER INVOKED BY: C:\Keil\C51\BIN\C51.EXE src\main.c BROWSE DEBUG OBJECTEXTEND CODE LISTINCLUDE SYMBOLS PRINT(.\main.
-lst) PREPRINT(.\main.i) OBJECT(main.obj)
line level source
1 #include "C8051F020.h"
1 =1 /*---------------------------------------------------------------------------
2 =1 ;
3 =1 ;
4 =1 ;
5 =1 ;
6 =1 ; FILE NAME : C8051F020.H
7 =1 ; TARGET MCUs : C8051F020, 'F021, 'F022, 'F023
8 =1 ; DESCRIPTION : Register/bit definitions for the C8051F02x product family.
9 =1 ;
10 =1 ; REVISION 1.1
11 =1 ;
12 =1 ;---------------------------------------------------------------------------*/
13 =1
14 =1 /* BYTE Registers */
15 =1 sfr P0 = 0x80; /* PORT 0 */
16 =1 sfr SP = 0x81; /* STACK POINTER */
17 =1 sfr DPL = 0x82; /* DATA POINTER - LOW BYTE */
18 =1 sfr DPH = 0x83; /* DATA POINTER - HIGH BYTE */
19 =1 sfr P4 = 0x84; /* PORT 4 */
20 =1 sfr P5 = 0x85; /* PORT 5 */
21 =1 sfr P6 = 0x86; /* PORT 6 */
22 =1 sfr PCON = 0x87; /* POWER CONTROL */
23 =1 sfr TCON = 0x88; /* TIMER CONTROL */
24 =1 sfr TMOD = 0x89; /* TIMER MODE */
25 =1 sfr TL0 = 0x8A; /* TIMER 0 - LOW BYTE */
26 =1 sfr TL1 = 0x8B; /* TIMER 1 - LOW BYTE */
27 =1 sfr TH0 = 0x8C; /* TIMER 0 - HIGH BYTE */
28 =1 sfr TH1 = 0x8D; /* TIMER 1 - HIGH BYTE */
29 =1 sfr CKCON = 0x8E; /* CLOCK CONTROL */
30 =1 sfr PSCTL = 0x8F; /* PROGRAM STORE R/W CONTROL */
31 =1 sfr P1 = 0x90; /* PORT 1 */
32 =1 sfr TMR3CN = 0x91; /* TIMER 3 CONTROL */
33 =1 sfr TMR3RLL = 0x92; /* TIMER 3 RELOAD REGISTER - LOW BYTE */
34 =1 sfr TMR3RLH = 0x93; /* TIMER 3 RELOAD REGISTER - HIGH BYTE */
35 =1 sfr TMR3L = 0x94; /* TIMER 3 - LOW BYTE */
36 =1 sfr TMR3H = 0x95; /* TIMER 3 - HIGH BYTE */
37 =1 sfr P7 = 0x96; /* PORT 7 */
38 =1 sfr SCON0 = 0x98; /* SERIAL PORT 0 CONTROL */
39 =1 sfr SBUF0 = 0x99; /* SERIAL PORT 0 BUFFER */
40 =1 sfr SPI0CFG = 0x9A; /* SERIAL PERIPHERAL INTERFACE 0 CONFIGURATION */
41 =1 sfr SPI0DAT = 0x9B; /* SERIAL PERIPHERAL INTERFACE 0 DATA */
42 =1 sfr ADC1 = 0x9C; /* ADC 1 DATA */
43 =1 sfr SPI0CKR = 0x9D; /* SERIAL PERIPHERAL INTERFACE 0 CLOCK RATE CONTROL */
44 =1 sfr CPT0CN = 0x9E; /* COMPARATOR 0 CONTROL */
45 =1 sfr CPT1CN = 0x9F; /* COMPARATOR 1 CONTROL */
46 =1 sfr P2 = 0xA0; /* PORT 2 */
47 =1 sfr EMI0TC = 0xA1; /* EMIF TIMING CONTROL */
48 =1 sfr EMI0CF = 0xA3; /* EXTERNAL MEMORY INTERFACE (EMIF) CONFIGURATION */
49 =1 sfr P0MDOUT = 0xA4; /* PORT 0 OUTPUT MODE CONFIGURATION */
50 =1 sfr P1MDOUT = 0xA5; /* PORT 1 OUTPUT MODE CONFIGURATION */
51 =1 sfr P2MDOUT = 0xA6; /* PORT 2 OUTPUT MODE CONFIGURATION */
52 =1 sfr P3MDOUT = 0xA7; /* PORT 3 OUTPUT MODE CONFIGURATION */
53 =1 sfr IE = 0xA8; /* INTERRUPT ENABLE */
C51 COMPILER V8.12 MAIN 04/03/2009 01:00:38 PAGE 2
54 =1 sfr SADDR0 = 0xA9; /* SERIAL PORT 0 SLAVE ADDRESS */
55 =1 sfr ADC1CN = 0xAA; /* ADC 1 CONTROL */
56 =1 sfr ADC1CF = 0xAB; /* ADC 1 ANALOG MUX CONFIGURATION */
57 =1 sfr AMX1SL = 0xAC; /* ADC 1 ANALOG MUX CHANNEL SELECT */
58 =1 sfr P3IF = 0xAD; /* PORT 3 EXTERNAL INTERRUPT FLAGS */
59 =1 sfr SADEN1 = 0xAE; /* SERIAL PORT 1 SLAVE ADDRESS MASK */
60 =1 sfr EMI0CN = 0xAF; /* EXTERNAL MEMORY INTERFACE CONTROL */
61 =1 sfr P3 = 0xB0; /* PORT 3 */
62 =1 sfr OSCXCN = 0xB1; /* EXTERNAL OSCILLATOR CONTROL */
63 =1 sfr OSCICN = 0xB2; /* INTERNAL OSCILLATOR CONTROL */
64 =1 sfr P74OUT = 0xB5; /* PORTS 4 - 7 OUTPUT MODE */
65 =1 sfr FLSCL = 0xB6; /* FLASH MEMORY TIMING PRESCALER */
66 =1 sfr FLACL = 0xB7; /* FLASH ACESS LIMIT */
67 =1 sfr IP = 0xB8; /* INTERRUPT PRIORITY */
68 =1 sfr SADEN0 = 0xB9; /* SERIAL PORT 0 SLAVE ADDRESS MASK */
69 =1 sfr AMX0CF = 0xBA; /* ADC 0 MUX CONFIGURATION */
70 =1 sfr AMX0SL = 0xBB; /* ADC 0 MUX CHANNEL SELECTION */
71 =1 sfr ADC0CF = 0xBC; /* ADC 0 CONFIGURATION */
72 =1 sfr P1MDIN = 0xBD; /* PORT 1 INPUT MODE */
73 =1 sfr ADC0L = 0xBE; /* ADC 0 DATA - LOW BYTE */
74 =1 sfr ADC0H = 0xBF; /* ADC 0 DATA - HIGH BYTE */
75 =1 sfr SMB0CN = 0xC0; /* SMBUS 0 CONTROL */
76 =1 sfr SMB0STA = 0xC1; /* SMBUS 0 STATUS */
77 =1 sfr SMB0DAT = 0xC2; /* SMBUS 0 DATA */
78 =1 sfr SMB0ADR = 0xC3; /* SMBUS 0 SLAVE ADDRESS */
79 =1 sfr ADC0GTL = 0xC4; /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */
80 =1 sfr ADC0GTH = 0xC5; /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */
81 =1 sfr ADC0LTL = 0xC6; /* ADC 0 LESS-THAN REGISTER - LOW BYTE */
82 =1 sfr ADC0LTH = 0xC7; /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */
83 =1 sfr T2CON = 0xC8; /* TIMER 2 CONTROL */
84 =1 sfr T4CON = 0xC9; /* TIMER 4 CONTROL */
85 =1 sfr RCAP2L = 0xCA; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
86 =1 sfr RCAP2H = 0xCB; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
87 =1 sfr TL2 = 0xCC; /* TIMER 2 - LOW BYTE */
88 =1 sfr TH2 = 0xCD; /* TIMER 2 - HIGH BYTE */
89 =1 sfr SMB0CR = 0xCF; /* SMBUS 0 CLOCK RATE */
90 =1 sfr PSW = 0xD0; /* PROGRAM STATUS WORD */
91 =1 sfr REF0CN = 0xD1; /* VOLTAGE REFERENCE 0 CONTROL */
92 =1 sfr DAC0L = 0xD2; /* DAC 0 REGISTER - LOW BYTE */
93 =1 sfr DAC0H = 0xD3; /* DAC 0 REGISTER - HIGH BYTE */
94 =1 sfr DAC0CN = 0xD4; /* DAC 0 CONTROL */
95 =1 sfr DAC1L = 0xD5; /* DAC 1 REGISTER - LOW BYTE */
96 =1 sfr DAC1H = 0xD6; /* DAC 1 REGISTER - HIGH BYTE */
97 =1 sfr DAC1CN = 0xD7; /* DAC 1 CONTROL */
98 =1 sfr PCA0CN = 0xD8; /* PCA 0 COUNTER CONTROL */
99 =1 sfr PCA0MD = 0xD9; /* PCA 0 COUNTER MODE */
100 =1 sfr PCA0CPM0 = 0xDA; /* CONTROL REGISTER FOR PCA 0 MODULE 0 */
101 =1 sfr PCA0CPM1 = 0xDB; /* CONTROL REGISTER FOR PCA 0 MODULE 1 */
102 =1 sfr PCA0CPM2 = 0xDC; /* CONTROL REGISTER FOR PCA 0 MODULE 2 */
103 =1 sfr PCA0CPM3 = 0xDD; /* CONTROL REGISTER FOR PCA 0 MODULE 3 */
104 =1 sfr PCA0CPM4 = 0xDE; /* CONTROL REGISTER FOR PCA 0 MODULE 4 */
105 =1 sfr ACC = 0xE0; /* ACCUMULATOR */
106 =1 sfr XBR0 = 0xE1; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 0 */
107 =1 sfr XBR1 = 0xE2; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 1 */
108 =1 sfr XBR2 = 0xE3; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 2 */
109 =1 sfr RCAP4L = 0xE4; /* TIMER 4 CAPTURE REGISTER - LOW BYTE */
110 =1 sfr RCAP4H = 0xE5; /* TIMER 4 CAPTURE REGISTER - HIGH BYTE */
111 =1 sfr EIE1 = 0xE6; /* EXTERNAL INTERRUPT ENABLE 1 */
112 =1 sfr EIE2 = 0xE7; /* EXTERNAL INTERRUPT ENABLE 2 */
113 =1 sfr ADC0CN = 0xE8; /* ADC 0 CONTROL */
114 =1 sfr PCA0L = 0xE9; /* PCA 0 TIMER - LOW BYTE */
115 =1 sfr PCA0CPL0 = 0xEA; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - LOW BYTE */
C51 COMPILER V8.12 MAIN 04/03/2009 01:00:38 PAGE 3
116 =1 sfr PCA0CPL1 = 0xEB; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - LOW BYTE */
117 =1 sfr PCA0CPL2 = 0xEC; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - LOW BYTE */
118 =1 sfr PCA0CPL3 = 0xED; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - LOW BYTE */
119 =1 sfr PCA0CPL4 = 0xEE; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - LOW BYTE */
120 =1 sfr RSTSRC = 0xEF; /* RESET SOURCE */
121 =1 sfr B = 0xF0; /* B REGISTER */
122 =1 sfr SCON1 = 0xF1; /* SERIAL PORT 1 CONTROL */
123 =1 sfr SBUF1 = 0xF2; /* SERAIL PORT 1 DATA */
124 =1 sfr SADDR1 = 0xF3; /* SERAIL PORT 1 */
125 =1 sfr TL4 = 0xF4; /* TIMER 4 DATA - LOW BYTE */
126 =1 sfr TH4 = 0xF5; /* TIMER 4 DATA - HIGH BYTE */
127 =1 sfr EIP1 = 0xF6; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
128 =1 sfr EIP2 = 0xF7; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */
129 =1 sfr SPI0CN = 0xF8; /* SERIAL PERIPHERAL INTERFACE 0 CONTROL */
130 =1 sfr PCA0H = 0xF9; /* PCA 0 TIMER - HIGH BYTE */
131 =1 sfr PCA0CPH0 = 0xFA; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - HIGH BYTE */
132 =1 sfr PCA0CPH1 = 0xFB; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - HIGH BYTE */
133 =1 sfr PCA0CPH2 = 0xFC; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - HIGH BYTE */
134 =1 sfr PCA0CPH3 = 0xFD; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - HIGH BYTE */
135 =1 sfr PCA0CPH4 = 0xFE; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - HIGH BYTE */
136 =1 sfr WDTCN = 0xFF; /* WATCHDOG TIMER CONTROL */
137 =1
138 =1
139 =1 /* BIT Registers */
140 =1
141 =1 /* TCON 0x88 */
142 =1 sbit TF1 = TCON ^ 7; /* TIMER 1 OVERFLOW FLAG */
143 =1 sbit TR1 = TCON ^ 6; /* TIMER 1 ON/OFF CONTROL */
144 =1 sbit TF0 = TCON ^ 5; /* TIMER 0 OVERFLOW FLAG */
145 =1 sbit TR0 = TCON ^ 4; /* TIMER 0 ON/OFF CONTROL */
146 =1 sbit IE1 = TCON ^ 3; /* EXT. INTERRUPT 1 EDGE FLAG */
147 =1 sbit IT1 = TCON ^ 2; /* EXT. INTERRUPT 1 TYPE */
148 =1 sbit IE0 = TCON ^ 1; /* EXT. INTERRUPT 0 EDGE FLAG */
149 =1 sbit IT0 = TCON ^ 0; /* EXT. INTERRUPT 0 TYPE */
150 =1
151 =1 /* SCON0 0x98 */
152 =1 sbit SM00 = SCON0 ^ 7; /* SERIAL MODE CONTROL BIT 0 */
153 =1 sbit SM10 = SCON0 ^ 6; /* SERIAL MODE CONTROL BIT 1 */
154 =1 sbit SM20 = SCON0 ^ 5; /* MULTIPROCESSOR COMMUNICATION ENABLE */
155 =1 sbit REN0 = SCON0 ^ 4; /* RECEIVE ENABLE */
156 =1 sbit TB80 = SCON0 ^ 3; /* TRANSMIT BIT 8 */
157 =1 sbit RB80 = SCON0 ^ 2; /* RECEIVE BIT 8 */
158 =1 sbit TI0 = SCON0 ^ 1; /* TRANSMIT INTERRUPT FLAG */
159 =1 sbit RI0 = SCON0 ^ 0; /* RECEIVE INTERRUPT FLAG */
160 =1
161 =1 /* IE 0xA8 */
162 =1 sbit EA = IE ^ 7; /* GLOBAL INTERRUPT ENABLE */
163 =1 sbit ET2 = IE ^ 5; /* TIMER 2 INTERRUPT ENABLE */
164 =1 sbit ES0 = IE ^ 4; /* UART0 INTERRUPT ENABLE */
165 =1 sbit ET1 = IE ^ 3; /* TIMER 1 INTERRUPT ENABLE */
166 =1 sbit EX1 = IE ^ 2; /* EXTERNAL INTERRUPT 1 ENABLE */
167 =1 sbit ET0 = IE ^ 1; /* TIMER 0 INTERRUPT ENABLE */
168 =1 sbit EX0 = IE ^ 0; /* EXTERNAL INTERRUPT 0 ENABLE */
169 =1
170 =1 /* IP 0xB8 */
171 =1 sbit PT2 = IP ^ 5; /* TIMER 2 PRIORITY */
172 =1 sbit PS = IP ^ 4; /* SERIAL PORT PRIORITY */
173 =1 sbit PT1 = IP ^ 3; /* TIMER 1 PRIORITY */
174 =1 sbit PX1 = IP ^ 2; /* EXTERNAL INTERRUPT 1 PRIORITY */
175 =1 sbit PT0 = IP ^ 1; /* TIMER 0 PRIORITY */
176 =1 sbit PX0 = IP ^ 0; /* EXTERNAL INTERRUPT 0 PRIORITY */
177 =1
C51 COMPILER V8.12 MAIN 04/03/2009 01:00:38 PAGE 4
178 =1 /* SMB0CN 0xC0 */
179 =1 sbit BUSY = SMB0CN ^ 7; /* SMBUS 0 BUSY */
180 =1 sbit ENSMB = SMB0CN ^ 6; /* SMBUS 0 ENABLE */
181 =1 sbit STA = SMB0CN ^ 5; /* SMBUS 0 START FLAG */
182 =1 sbit STO = SMB0CN ^ 4; /* SMBUS 0 STOP FLAG */
183 =1 sbit SI = SMB0CN ^ 3; /* SMBUS 0 INTERRUPT PENDING FLAG */
184 =1 sbit AA = SMB0CN ^ 2; /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */
185 =1 sbit SMBFTE = SMB0CN ^ 1; /* SMBUS 0 FREE TIMER ENABLE */
186 =1 sbit SMBTOE = SMB0CN ^ 0; /* SMBUS 0 TIMEOUT ENABLE */
187 =1
188 =1 /* T2CON 0xC8 */
189 =1 sbit TF2 = T2CON ^ 7; /* TIMER 2 OVERFLOW FLAG */
190 =1 sbit EXF2 = T2CON ^ 6; /* EXTERNAL FLAG */
191 =1 sbit RCLK0 = T2CON ^ 5; /* UART0 RX CLOCK SOURCE */
192 =1 sbit TCLK0 = T2CON ^ 4; /* UART0 TX CLOCK SOURCE */
193 =1 sbit EXEN2 = T2CON ^ 3; /* TIMER 2 EXTERNAL ENABLE FLAG */
194 =1 sbit TR2 = T2CON ^ 2; /* TIMER 2 ON/OFF CONTROL */
195 =1 sbit CT2 = T2CON ^ 1; /* TIMER OR COUNTER SELECT */
196 =1 sbit CPRL2 = T2CON ^ 0; /* CAPTURE OR RELOAD SELECT */
197 =1
198 =1 /* PSW */
199 =1 sbit CY = PSW ^ 7; /* CARRY FLAG */
200 =1 sbit AC = PSW ^ 6; /* AUXILIARY CARRY FLAG */
201 =1 sbit F0 = PSW ^ 5; /* USER FLAG 0 */
202 =1 sbit RS1 = PSW ^ 4; /* REGISTER BANK SELECT 1 */
203 =1 sbit RS0 = PSW ^ 3; /* REGISTER BANK SELECT 0 */
204 =1 sbit OV = PSW ^ 2; /* OVERFLOW FLAG */
205 =1 sbit F1 = PSW ^ 1; /* USER FLAG 1 */
206 =1 sbit P = PSW ^ 0; /* ACCUMULATOR PARITY FLAG */
207 =1
208 =1 /* PCA0CN D8H */
209 =1 sbit CF = PCA0CN ^ 7; /* PCA 0 COUNTER OVERFLOW FLAG */
210 =1 sbit CR = PCA0CN ^ 6; /* PCA 0 COUNTER RUN CONTROL BIT */
211 =1 sbit CCF4 = PCA0CN ^ 4; /* PCA 0 MODULE 4 INTERRUPT FLAG */
212 =1 sbit CCF3 = PCA0CN ^ 3; /* PCA 0 MODULE 3 INTERRUPT FLAG */
213 =1 sbit CCF2 = PCA0CN ^ 2; /* PCA 0 MODULE 2 INTERRUPT FLAG */
214 =1 sbit CCF1 = PCA0CN ^ 1; /* PCA 0 MODULE 1 INTERRUPT FLAG */
215 =1 sbit CCF0 = PCA0CN ^ 0; /* PCA 0 MODULE 0 INTERRUPT FLAG */
216 =1
217 =1 /* ADC0CN E8H */
218 =1 sbit AD0EN = ADC0CN ^ 7; /* ADC 0 ENABLE */
219 =1 sbit AD0TM = ADC0CN ^ 6; /* ADC 0 TRACK MODE */
220 =1 sbit AD0INT = ADC0CN ^ 5; /* ADC 0 CONVERISION COMPLETE INTERRUPT FLAG */
221 =1 sbit AD0BUSY = ADC0CN ^ 4; /* ADC 0 BUSY FLAG */
222 =1 sbit AD0CM1 = ADC0CN ^ 3; /* ADC 0 START OF CONVERSION MODE BIT 1 */
223 =1 sbit AD0CM0 = ADC0CN ^ 2; /* ADC 0 START OF CONVERSION MODE BIT 0 */
224 =1 sbit AD0WINT = ADC0CN ^ 1; /* ADC 0 WINDOW COMPARE INTERRUPT FLAG */
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