📄 intr.c
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irq2++;
}
// Mask and clear interrupt
mask = 1 << (irq2 - IRQ_EINT4 + 4);
SETREG32(&g_pPortRegs->EINTMASK, mask);
OUTREG32(&g_pPortRegs->EINTPEND, mask);
// Clear primary interrupt
mask = 1 << irq;
OUTREG32(&g_pIntrRegs->SRCPND, mask);
OUTREG32(&g_pIntrRegs->INTPND, mask);
// From now we care about this irq
irq = irq2;
}
else if(irq == IRQ_CAM)
{
if(INREG32(&g_pIntrRegs->SUBSRCPND) & (1<<IRQ_SUB_CAM_C))
{
SETREG32(&g_pIntrRegs->INTSUBMSK, (1<<IRQ_SUB_CAM_C));
SETREG32(&g_pIntrRegs->INTMSK, (1<<IRQ_CAM));
OUTREG32(&g_pIntrRegs->SUBSRCPND, (1<<IRQ_SUB_CAM_C));
OUTREG32(&g_pIntrRegs->SRCPND, (1<<IRQ_CAM));
OUTREG32(&g_pIntrRegs->INTPND,(1<<IRQ_CAM));
//RETAILMSG(1,(TEXT("IRQ_CAM Codec\r\n")));
}
else if(INREG32(&g_pIntrRegs->SUBSRCPND) & (1<<IRQ_SUB_CAM_P))
{
SETREG32(&g_pIntrRegs->INTSUBMSK, (1<<IRQ_SUB_CAM_P));
SETREG32(&g_pIntrRegs->INTMSK, (1<<IRQ_CAM));
OUTREG32(&g_pIntrRegs->SUBSRCPND, (1<<IRQ_SUB_CAM_P));
OUTREG32(&g_pIntrRegs->SRCPND, (1<<IRQ_CAM));
OUTREG32(&g_pIntrRegs->INTPND,(1<<IRQ_CAM));
//RETAILMSG(1,(TEXT("PreView\r\n")));
}
else
{
SETREG32(&g_pIntrRegs->INTSUBMSK, (1<<IRQ_SUB_CAM_C)|(1<<IRQ_SUB_CAM_P));
SETREG32(&g_pIntrRegs->INTMSK, (1<<IRQ_CAM));
SETREG32(&g_pIntrRegs->SUBSRCPND, (1<<IRQ_SUB_CAM_C)|(1<<IRQ_SUB_CAM_P));
OUTREG32(&g_pIntrRegs->SRCPND, (1<<IRQ_CAM));
OUTREG32(&g_pIntrRegs->INTPND,(1<<IRQ_CAM));
// RETAILMSG(1,(TEXT("nop\r\n")));
return SYSINTR_NOP;
}
}
#ifdef DVS_EN
#if (DVS_METHOD == 1)
else if(irq == IRQ_LCD)
{
VSYNCINTR = TRUE;
if ( IDLEflag == FALSE )
{
// 4.1 Mask LCD VSYNC Interrupt
// for frame interrupt
if(INREG32(&g_pIntrRegs->SUBSRCPND) & (1 << IRQ_SUB_LCD3) )
{
SETREG32(&g_pLCDRegs->VIDINTCON, 1); // disable LCD interrupt
SETREG32(&g_pIntrRegs->INTSUBMSK, (1 << IRQ_SUB_LCD3) ); // masking LCD3 sub interrupt
SETREG32(&g_pIntrRegs->INTMSK, (1 << IRQ_LCD) ); // masking LCD interrupt
OUTREG32(&g_pIntrRegs->SUBSRCPND, (1<<IRQ_SUB_LCD3) ); // Clear LCD3 sub source pending register bit
OUTREG32(&g_pIntrRegs->SRCPND, (1<<IRQ_LCD) ); // Clear LCD source pending register bit
OUTREG32(&g_pIntrRegs->INTPND, (1<<IRQ_LCD) ); // Clear LCD interrupt register bit
// why use READ & WRITE process before?
// if( INREG32(&g_pIntrRegs->INTPND) & ( 0x1 << IRQ_LCD)) OUTREG32(&g_pIntrRegs->INTPND, 0x1 << IRQ_LCD);
if (INREG32(&g_pLCDRegs->VIDCON1) & LCD_VSTATUS ) // Check VSync Area(VSTATUS Field)
{
// RETAILMSG(1,(TEXT("+")));
}
else
{
CurrStateIdle = FALSE;
// OUTREG32(&g_pLCDRegs->VIDCON0, INREG32(&g_pLCDRegs->VIDCON0) & ~(0x3)); //Disable LCD Output, ENVID & ENVID_F, no need in 2443
// 4.2 Return Voltage
ChangeVoltage(HIGHVOLTAGE);
// 4.3 Delay
for(i=0;i<VOLTAGEDELAY;i++)
{
INREG32(&g_pPortRegs->GPFDAT); // for loop operation, just read.
}
// 4.4 DVS OFF
// 4:4:4 -> 1:4:4 -> 1:2:4
// 6:6:6 -> 1:6:6 -> 1:3:6
// 8:8:8 -> 1:8:8 -> 1:4:8
DVS_OFF();
g_oalIoCtlClockSpeed = S3C2443_FCLK;
switch ( HCLKDIV )
{
case 4:
CLKDIV124();
break;
case 6:
CLKDIV136();
break;
case 8:
CLKDIV148();
break;
}
clkval = (UINT8)(((float)S3C2443_HCLK/(float)(g_hsync_cnt*g_vclk_cnt*g_lcd_frame_rate*2))+0.5)-1;
g_pLCDRegs->VIDCON0 &= ~(0x3f <<VIDCON0_CLKVAL_F_SHIFT); // clock value clear
g_pLCDRegs->VIDCON0 |= (clkval <<VIDCON0_CLKVAL_F_SHIFT); // clock resetting
// Enable LCD Output, and reset LCD Clock, no need in 2443
// g_pLCDRegs->VIDCON0 |= 0x3;
// RETAILMSG(1,(TEXT("N"), IDLEflag));
}
}// end if (IRQ_SUB_LCD3)
} // end (IDLEflag == FALSE)
else // (IDLEflag == TRUE)
{
// 2.1 Mask LCD VSYNC Interrupt
// for frame interrupt
if(INREG32(&g_pIntrRegs->SUBSRCPND) & (1 << IRQ_SUB_LCD3) )
{
SETREG32(&g_pLCDRegs->VIDINTCON, 1); // disable LCD interrupt
SETREG32(&g_pIntrRegs->INTSUBMSK, (1 << IRQ_SUB_LCD3) );
SETREG32(&g_pIntrRegs->INTMSK, (1 << IRQ_LCD) );
OUTREG32(&g_pIntrRegs->SUBSRCPND, (1<<IRQ_SUB_LCD3) );
OUTREG32(&g_pIntrRegs->SRCPND, (1<<IRQ_LCD) );
OUTREG32(&g_pIntrRegs->INTPND, (1<<IRQ_LCD) );
// why use READ & WRITE process before?
// if( INREG32(&g_pIntrRegs->INTPND) & ( 0x1 << IRQ_LCD)) OUTREG32(&g_pIntrRegs->INTPND, 0x1 << IRQ_LCD);
if (INREG32(&g_pLCDRegs->VIDCON1) & LCD_VSTATUS ) // Check VSync Area(VSTATUS Field)
{
// RETAILMSG(1,(TEXT("-")));
}
else
{
CurrStateIdle = TRUE;
//Disable LCD Output, ENVID & ENVID_F, no need in 2443
// OUTREG32(&g_pLCDRegs->VIDCON0, INREG32(&g_pLCDRegs->VIDCON0) & ~(0x3));
// DVS ON (1:2:4 -> 4:4:4)
switch ( HCLKDIV )
{
case 2:
CLKDIV144();
break;
case 3:
CLKDIV166();
break;
case 4:
CLKDIV188();
break;
}
DVS_ON();
g_oalIoCtlClockSpeed = S3C2443_PCLK;
// 2.4 Drop Voltage
ChangeVoltage(LOWVOLTAGE);
clkval = (UINT8)(((float)S3C2443_HCLK/(float)(g_hsync_cnt*g_vclk_cnt*g_lcd_frame_rate*2))+0.5)-1;
g_pLCDRegs->VIDCON0 &= ~(0x3f <<VIDCON0_CLKVAL_F_SHIFT); // clock value clear
g_pLCDRegs->VIDCON0 |= (clkval <<VIDCON0_CLKVAL_F_SHIFT); // clock resetting
// Enable LCD Output, and reset LCD Clock
// g_pLCDRegs->VIDCON0 |= 0x3;
// RETAILMSG(1,(TEXT("I"),IDLEflag));
}
} // end if (IRQ_SUB_LCD3)
} // end (IDLEflag == TRUE)
sysIntr = SYSINTR_NOP;
}
#elif (DVS_METHOD == 3)
else if( irq == IRQ_LCD )
{
VSYNCINTR = TRUE;
if ( CurrentState == Active )
{
if(INREG32(&g_pIntrRegs->SUBSRCPND) & (1 << IRQ_SUB_LCD3) )
{
SETREG32(&g_pIntrRegs->INTSUBMSK, (1 << IRQ_SUB_LCD3) );
SETREG32(&g_pIntrRegs->INTMSK, (1 << IRQ_LCD) );
OUTREG32(&g_pIntrRegs->SUBSRCPND, (1 << IRQ_SUB_LCD3) );
OUTREG32(&g_pIntrRegs->SRCPND, (1 << IRQ_LCD) );
OUTREG32(&g_pIntrRegs->INTPND, (1 << IRQ_LCD) );
// why use READ & WRITE process before?
// if( INREG32(&g_pIntrRegs->INTPND) & ( 0x1 << IRQ_LCD)) OUTREG32(&g_pIntrRegs->INTPND, 0x1 << IRQ_LCD);
if (INREG32(&g_pLCDRegs->VIDCON1) & LCD_VSTATUS ) // Check VSync Area(VSTATUS Field)
{
// RETAILMSG(1,(TEXT("-BD-")));
}
else
{
//Disable LCD Output, ENVID & ENVID_F, 2443 no more need disable LCD output
// OUTREG32(&g_pLCDRegs->VIDCON0, INREG32(&g_pLCDRegs->VIDCON0) & ~(0x3));
ChangeVoltage(HIGHVOLTAGE);
for(i=0;i<VOLTAGEDELAY;i++) { INREG32(&g_pPortRegs->GPFDAT); } // for loop operation, just read.
DVS_OFF();
g_oalIoCtlClockSpeed = S3C2443_FCLK;
switch ( HCLKDIV )
{
case 4:
CLKDIV124();
break;
case 6:
CLKDIV136();
break;
case 8:
CLKDIV148();
break;
}
clkval = (UINT8)(((float)S3C2443_HCLK/(float)(g_hsync_cnt*g_vclk_cnt*g_lcd_frame_rate*2))+0.5)-1;
g_pLCDRegs->VIDCON0 &= ~(0x3f << VIDCON0_CLKVAL_F_SHIFT); // clock value clear
g_pLCDRegs->VIDCON0 |= (clkval << VIDCON0_CLKVAL_F_SHIFT); // clock resetting
// Enable LCD Output, and reset LCD Clock, no need in 2443
// g_pLCDRegs->VIDCON0 |= 0x3;
// RETAILMSG(1,(TEXT("-a-")));
}
}// end if (IRQ_SUB_LCD3)
} // end if CurrentState == Active)
else if ( CurrentState == SlowActive )
{
VSYNCINTR = TRUE;
if ( IDLEflag == FALSE )
{
if(INREG32(&g_pIntrRegs->SUBSRCPND) & (1 << IRQ_SUB_LCD3) )
{
SETREG32(&g_pIntrRegs->INTSUBMSK, (1 << IRQ_SUB_LCD3) );
SETREG32(&g_pIntrRegs->INTMSK, (1 << IRQ_LCD) );
OUTREG32(&g_pIntrRegs->SUBSRCPND, (1 << IRQ_SUB_LCD3) );
OUTREG32(&g_pIntrRegs->SRCPND, (1 << IRQ_LCD) );
OUTREG32(&g_pIntrRegs->INTPND, (1 << IRQ_LCD) );
// why use READ & WRITE process before?
// if( INREG32(&g_pIntrRegs->INTPND) & ( 0x1 << IRQ_LCD)) OUTREG32(&g_pIntrRegs->INTPND, 0x1 << IRQ_LCD);
if (INREG32(&g_pLCDRegs->VIDCON1) & LCD_VSTATUS ) // Check VSync Area(VSTATUS Field)
{
// RETAILMSG(1,(TEXT("-BD-")));
}
else
{
CurrStateIdle = FALSE;
//Disable LCD Output, ENVID & ENVID_F, no more need
// OUTREG32(&g_pLCDRegs->VIDCON0, INREG32(&g_pLCDRegs->VIDCON0) & ~(0x3));
ChangeVoltage(HIGHVOLTAGE);
for(i=0;i<VOLTAGEDELAY;i++) { INREG32(&g_pPortRegs->GPFDAT); } // for loop operation, just read.
DVS_OFF();
g_oalIoCtlClockSpeed = S3C2443_FCLK;
switch ( HCLKDIV )
{
case 4:
CLKDIV124();
break;
case 6:
CLKDIV136();
break;
case 8:
CLKDIV148();
break;
}
clkval = (UINT8)(((float)S3C2443_HCLK/(float)(g_hsync_cnt*g_vclk_cnt*g_lcd_frame_rate*2))+0.5)-1;
g_pLCDRegs->VIDCON0 &= ~(0x3f << VIDCON0_CLKVAL_F_SHIFT); // clock value clear
g_pLCDRegs->VIDCON0 |= (clkval << VIDCON0_CLKVAL_F_SHIFT); // clock resetting
// Enable LCD Output, and reset LCD Clock, no need in 2443
// g_pLCDRegs->VIDCON0 |= 0x3;
}
// RETAILMSG(1,(TEXT("-F-")));
} // end if (IRQ_SUB_LCD3)
} // end if (IDLEflag == FALSE)
else //if ( IDLEflag == TRUE )
{
if(INREG32(&g_pIntrRegs->SUBSRCPND) & (1 << IRQ_SUB_LCD3) )
{
SETREG32(&g_pIntrRegs->INTSUBMSK, (1 << IRQ_SUB_LCD3) );
SETREG32(&g_pIntrRegs->INTMSK, (1 << IRQ_LCD) );
OUTREG32(&g_pIntrRegs->SUBSRCPND, (1 << IRQ_SUB_LCD3) );
OUTREG32(&g_pIntrRegs->SRCPND, (1 << IRQ_LCD) );
OUTREG32(&g_pIntrRegs->INTPND, (1 << IRQ_LCD) );
// why use READ & WRITE process before?
// if( INREG32(&g_pIntrRegs->INTPND) & ( 0x1 << IRQ_LCD)) OUTREG32(&g_pIntrRegs->INTPND, 0x1 << IRQ_LCD);
if (INREG32(&g_pLCDRegs->VIDCON1) & LCD_VSTATUS ) // Check VSync Area(VSTATUS Field)
{
// RETAILMSG(1,(TEXT("-BD-")));
}
else
{
CurrStateIdle = TRUE;
//Disable LCD Output, ENVID & ENVID_F, no need in 2443
// OUTREG32(&g_pLCDRegs->VIDCON0, INREG32(&g_pLCDRegs->VIDCON0) & ~(0x3));
switch ( HCLKDIV )
{
case 2:
CLKDIV144();
break;
case 3:
CLKDIV166();
break;
case 4:
CLKDIV188();
break;
}
DVS_ON();
g_oalIoCtlClockSpeed = S3C2443_PCLK;
ChangeVoltage(LOWVOLTAGE);
clkval = (UINT8)(((float)S3C2443_HCLK/(float)(g_hsync_cnt*g_vclk_cnt*g_lcd_frame_rate*2))+0.5)-1;
g_pLCDRegs->VIDCON0 &= ~(0x3f <<VIDCON0_CLKVAL_F_SHIFT); // clock value clear
g_pLCDRegs->VIDCON0 |= (clkval <<VIDCON0_CLKVAL_F_SHIFT); // clock resetting
// Enable LCD Output, and reset LCD Clock, no need in 2443
// g_pLCDRegs->VIDCON0 |= 0x3;
}
// RETAILMSG(1,(TEXT("-T-")));
} // end if (IRQ_SUB_LCD3)
} // end if (IDLEflag == TRUE)
} // end if ( CurrentState == SlowActive )
sysIntr = SYSINTR_NOP;
} // end if( irq == IRQ_LCD )
#endif //(DVS_METHOD == 3)
#endif //DVS_EN
else if(irq == IRQ_DMA)
{
//RETAILMSG(1,(TEXT("DMA\n")));
if(INREG32(&g_pIntrRegs->SUBSRCPND) & (1<<IRQ_SUB_DMA0))
{
SETREG32(&g_pIntrRegs->INTSUBMSK, (1<<IRQ_SUB_DMA0));
OUTREG32(&g_pIntrRegs->SUBSRCPND, (1<<IRQ_SUB_DMA0));
irq = IRQ_DMA0;
}
else if(INREG32(&g_pIntrRegs->SUBSRCPND) & (1<<IRQ_SUB_DMA1))
{
//RETAILMSG(1,(TEXT("DMA1\n")));
SETREG32(&g_pIntrRegs->INTSUBMSK, (1<<IRQ_SUB_DMA1));
OUTREG32(&g_pIntrRegs->SUBSRCPND, (1<<IRQ_SUB_DMA1));
irq = IRQ_DMA1;
}
else if(INREG32(&g_pIntrRegs->SUBSRCPND) & (1<<IRQ_SUB_DMA2))
{
RETAILMSG(1,(TEXT("DMA2\n")));
SETREG32(&g_pIntrRegs->INTSUBMSK, (1<<IRQ_SUB_DMA2));
OUTREG32(&g_pIntrRegs->SUBSRCPND, (1<<IRQ_SUB_DMA2));
irq = IRQ_DMA2;
}
else if(INREG32(&g_pIntrRegs->SUBSRCPND) & (1<<IRQ_SUB_DMA3))
{
SETREG32(&g_pIntrRegs->INTSUBMSK, (1<<IRQ_SUB_DMA3));
OUTREG32(&g_pIntrRegs->SUBSRCPND, (1<<IRQ_SUB_DMA3));
irq = IRQ_DMA3;
}
else if(INREG32(&g_pIntrRegs->SUBSRCPND) & (1<<IRQ_SUB_DMA4))
{
SETREG32(&g_pIntrRegs->INTSUBMSK, (1<<IRQ_SUB_DMA4));
OUTREG32(&g_pIntrRegs->SUBSRCPND, (1<<IRQ_SUB_DMA4));
irq = IRQ_DMA4;
}
else if(INREG32(&g_pIntrRegs->SUBSRCPND) & (1<<IRQ_SUB_DMA5))
{
SETREG32(&g_pIntrRegs->INTSUBMSK, (1<<IRQ_SUB_DMA5));
OUTREG32(&g_pIntrRegs->SUBSRCPND, (1<<IRQ_SUB_DMA5));
irq = IRQ_DMA5;
}
OUTREG32(&g_pIntrRegs->SRCPND, (1<<IRQ_DMA));
OUTREG32(&g_pIntrRegs->INTPND,(1<<IRQ_DMA));
}
else if(irq == IRQ_CFCON)
{
if ( !(g_pATAPIRegs->ATA_IRQ & 0x1))
{
g_pATAPIRegs->ATA_IRQ = 0xff;
OUTREG32(&g_pIntrRegs->SRCPND, 1<<IRQ_CFCON );
OUTREG32(&g_pIntrRegs->INTPND, 1<<IRQ_CFCON );
return SYSINTR_NOP;
}
g_pATAPIRegs->ATA_IRQ_MASK = 0xffffffff;
g_pATAPIRegs->ATA_IRQ = 0xff;
SETREG32(&g_pIntrRegs->INTMSK, 1<<IRQ_CFCON );
OUTREG32(&g_pIntrRegs->SRCPND, 1<<IRQ_CFCON );
OUTREG32(&g_pIntrRegs->INTPND, 1<<IRQ_CFCON );
}
else {
// Mask and clear interrupt
mask = 1 << irq;
SETREG32(&g_pIntrRegs->INTMSK, mask);
OUTREG32(&g_pIntrRegs->SRCPND, mask);
OUTREG32(&g_pIntrRegs->INTPND, mask);
}
// First find if IRQ is claimed by chain
sysIntr = NKCallIntChain((UCHAR)irq);
if (sysIntr == SYSINTR_CHAIN || !NKIsSysIntrValid(sysIntr)) {
// IRQ wasn't claimed, use static mapping
sysIntr = OALIntrTranslateIrq(irq);
}
}
//g_oalLastSysIntr = sysIntr;
return sysIntr;
}
//------------------------------------------------------------------------------
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