bsp_cfg.h

2443 wince5.0 bsp, source code

//
// Copyright (c) Microsoft Corporation.  All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
//------------------------------------------------------------------------------
//
//  File:  bsp_cfg.h
//
//  This file contains system constant specific for SMDK2443 board.
//
#ifndef __BSP_CFG_H
#define __BSP_CFG_H

//------------------------------------------------------------------------------
//
//  Define:  BSP_DEVICE_PREFIX
//
//  Prefix used to generate device name for bootload/KITL
//
#define BSP_DEVICE_PREFIX       "SMDK2443"        // Device name prefix
//------------------------------------------------------------------------------
// Board version
//------------------------------------------------------------------------------
// If you use CPU which is EVT0 version, define only EVT0.
// We recommend newer CPU board.
// Now, you define only in smdk2443.bat file. This definition is not need.
//#define	EVT1		//#define EVT0

//------------------------------------------------------------------------------
// System Tick define
//------------------------------------------------------------------------------
// There are two type system ticks. choose only one type.
// Fixed tick means that tick interrupt is occurred every 1ms.
// Variable tick means that timer interrupt period is changed when power mode is in idle.
#define FIXEDTICK	
//#define VARTICK

//------------------------------------------------------------------------------
// Board clock
//------------------------------------------------------------------------------
#define D1_2			0x0
#define D1_4			0x1
#define D1_8			0x2
#define D1_16			0x3
#define D2				2
#define D4				4
#define D8				8
#define D16				16

//#define S3C2443_FCLK           400000000           // 399.65MHz


#if 1
#define S3C2443_FCLK           534000000           // 534.00MHz
#define S3C2443_HCLK           (S3C2443_FCLK/4)   // divisor 4
#define S3C2443_PCLK           (S3C2443_FCLK/8)   // divisor 2
#define S3C2443_SCLK           96000000
#define HCLKDIV					4
#else

#define S3C2443_BASE_REG_VA_CLOCK_POWER	0xB1000000
#define PLLVALUE			(((S3C2443_CLKPWR_REG*)(S3C2443_BASE_REG_VA_CLOCK_POWER))->MPLLCON)
#define CLKDIV				(((S3C2443_CLKPWR_REG*)(S3C2443_BASE_REG_VA_CLOCK_POWER))->CLKDIV0)

#define M_DIV ((PLLVALUE >> 16) & 0xff)
#define P_DIV ((PLLVALUE >> 8) & 0x3)
#define S_DIV ((PLLVALUE >> 0) & 0x1)

#define ARMDIVN ((CLKDIV >> 9) & 0xf)


#define ARMDIV				(ARMDIVN == 0 ?	1 : \
								(ARMDIVN == 8 ? 2 : \
									(ARMDIVN == 2 ? 3 : \
										(ARMDIVN == 9 ? 4 : \
											(ARMDIVN == 10 ? 6 : \
												(ARMDIVN == 11 ? 8 : \
													(ARMDIVN == 13 ? 12 : \
														(ARMDIVN == 15 ? 16 : 1) \
													) \
												) \
											) \
										) \
									) \
								) \
							)
									

#define PREDIV ((CLKDIV >> 4) & 0x3)
#define HCLKDIV				((CLKDIV>>0) & 0x3)
#define PCLKDIV				((CLKDIV>>2) & 0x1)
#define HALFHCLK			((CLKDIV>>3) & 0x1)

#define S3C2443_FOUT   		(2 * (M_DIV + 8L) * (12000000L / (P_DIV) / (1<<S_DIV )))
#define S3C2443_FCLK		(S3C2443_FOUT  / ARMDIV )
#define S3C2443_HCLK        (S3C2443_FOUT / (PREDIV+1) / (HCLKDIV+1))   // divisor 4
#define S3C2443_PCLK        (S3C2443_HCLK / (PCLKDIV+1))  // divisor 2


#define EPLLVALUE			(((S3C2443_CLKPWR_REG*)(S3C2443_BASE_REG_VA_CLOCK_POWER))->EPLLCON)
#define EPLL_M_DIV ((EPLLVALUE >> 16) & 0xff)
#define EPLL_P_DIV ((EPLLVALUE >> 8) & 0x3f)
#define EPLL_S_DIV ((EPLLVALUE >> 0) & 0x3)
#define S3C2443_SCLK   		((EPLL_M_DIV + 8L) * (12000000L / (EPLL_P_DIV+2) / (1<<EPLL_S_DIV )))

#endif

#define SYS_TIMER_DIVIDER	D2

#ifdef VARTICK
#define PRESCALER			((S3C2443_PCLK/(1000000*SYS_TIMER_DIVIDER)) - 1)
#define OEM_CLOCK_FREQ		(S3C2443_PCLK/(PRESCALER+1)/SYS_TIMER_DIVIDER)
// Timer count for 1 ms
#define OEM_COUNT_1MS       (OEM_CLOCK_FREQ / 1000)	// OEM_CLOCK_FREQ = 1000000, 1000000/1000 => 1000 = 1 msec
#define RESCHED_PERIOD      1		// 10				// Reschedule period in ms
#else	// FIXEDTICK
#define PRESCALER			14   //25-1 // 125-1
#define OEM_COUNT_1MS		2224  //1335-1  // 267-1
#define RESCHED_PERIOD      1
#endif
//------------------------------------------------------------------------------
// Debug UART1
//------------------------------------------------------------------------------

#define BSP_UART1_ULCON         0x03                // 8 bits, 1 stop, no parity
#define BSP_UART1_UCON          0x0005              // pool mode, PCLK for UART
#define BSP_UART1_UFCON         0x00                // disable FIFO
#define BSP_UART1_UMCON         0x00                // disable auto flow control
#define BSP_UART1_UBRDIV        (S3C2443_PCLK/(115200*16) - 1)

//------------------------------------------------------------------------------
// Static SYSINTR Mapping for driver.
#define SYSINTR_OHCI            (SYSINTR_FIRMWARE+1)
#define SYSINTR_HSMMC            (SYSINTR_FIRMWARE+2)

// -----------------------------------------------------------------------------
// define For DVS, MAX1718 Preset Value
#define V80	80
#define V85	85
#define V90	90
#define V95	95
#define V100	100
#define V105	105
#define V110	110
#define V115	115
#define V120	120
#define V125	125
#define V130	130
#define V135	135
#define V140	140
#define V145	145
#define V150	150
#define V155	155
#define V160	160
#define V165	165
#define V170	170
#define V175	175

#define DVS_METHOD	2  //1:DVS_ON with VSYNC, 2:DVS_ON in idle mode(not change HCLK), 3:mixed
#define USESWPWSAVING	1
#define MVAL_USED		0
#define HIGHVOLTAGE		V135
#define MIDVOLTAGE		V120	
#define LOWVOLTAGE		V100
#define VOLTAGEDELAY	16000

#define Eval_Probe		1

#define DVSON		0x1
#define HCLKHALF	0x2
#define ACTIVE		0x4
#define DeepIdle	(DVSON|HCLKHALF)
#define NIdle		(DVSON)
#define LazyActive	(ACTIVE|DVSON|HCLKHALF)
#define SlowActive	(ACTIVE|DVSON)
#define Active		(ACTIVE)
//------------------------------------------------------------

#endif