📄 smscir.h
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//
// Copyright (c) Microsoft Corporation. All rights reserved.
// Copyright 2005 OSR, Open Systems Resources, Inc. All rights Reserved.
//
// Module Name:
//
// smscir.h
//
// Abstract:
//
// Author:
//
// Revision History:
//
#ifndef SmscIrH
#define SmscIrH
#include <ntddk.h>
#include <wdf.h>
#include <ntintsafe.h>
#include <initguid.h>
#include <wdmguid.h>
#include <ntintsafe.h>
#include <irclass_ioctl.h>
#include <specstrings.h>
#include <limits.h>
//
// Our device type. Randomly chosen from the "non-reserved" range
//
#define FILE_DEVICE_SMSCIR 0x0F70
// {064F8C82-77B2-445e-B85D-C4E20F942FE1}
DEFINE_GUID(GUID_DEVINTERFACE_IRPORT,
0x64f8c82, 0x77b2, 0x445e, 0xb8, 0x5d, 0xc4, 0xe2, 0xf, 0x94, 0x2f, 0xe1);
//
// Debugging Output Levels
//
#ifndef TRACE_LEVEL_INFORMATION
#define TRACE_LEVEL_NONE 0 // Tracing is not on
#define TRACE_LEVEL_FATAL 1 // Abnormal exit or termination
#define TRACE_LEVEL_ERROR 2 // Severe errors that need logging
#define TRACE_LEVEL_WARNING 3 // Warnings such as allocation failure
#define TRACE_LEVEL_INFORMATION 4 // Includes non-error cases(e.g.,Entry-Exit)
#define TRACE_LEVEL_VERBOSE 5 // Detailed traces from intermediate steps
#define TRACE_LEVEL_RESERVED6 6
#define TRACE_LEVEL_RESERVED7 7
#define TRACE_LEVEL_RESERVED8 8
#define TRACE_LEVEL_RESERVED9 9
#endif // TRACE_LEVEL_INFORMATION
//
// WPP_TRACING is enabled or disabled in the SOURCES file
//
#ifdef WPP_TRACING
#define WPP_CONTROL_GUIDS \
WPP_DEFINE_CONTROL_GUID(SMSCIRTRACE,(E4FC8EBB,5287,4aa5,8585,C524C9A00DCC), \
WPP_DEFINE_BIT(SMSCDBG_PNP_INFO) \
WPP_DEFINE_BIT(SMSCDBG_IOCTL_INFO) \
WPP_DEFINE_BIT(SMSCDBG_CREATE_CLOSE_INFO) \
WPP_DEFINE_BIT(SMSCDBG_RECEIVE_INFO) \
WPP_DEFINE_BIT(SMSCDBG_INIT_INFO) \
WPP_DEFINE_BIT(SMSCDBG_WAKE_INFO) \
WPP_DEFINE_BIT(SMSCDBG_TRANSMIT_INFO) \
)
#define WPP_LEVEL_FLAGS_LOGGER(lvl,flags) \
WPP_LEVEL_LOGGER(flags)
#define WPP_LEVEL_FLAGS_ENABLED(lvl, flags) \
(WPP_LEVEL_ENABLED(flags) && WPP_CONTROL(WPP_BIT_ ## flags).Level >= lvl)
#else // WPP_TRACING
extern ULONG DefaultDebugLevel;
extern ULONG DefaultDebugFlags;
#define SMSCDBG_PNP_INFO 0x00000001
#define SMSCDBG_IOCTL_INFO 0x00000002
#define SMSCDBG_CREATE_CLOSE_INFO 0x00000004
#define SMSCDBG_RECEIVE_INFO 0x00000008
#define SMSCDBG_INIT_INFO 0x00000010
#define SMSCDBG_WAKE_INFO 0x00000020
#define SMSCDBG_TRANSMIT_INFO 0x00000040
#define SmscIrTracePrint(_level_,_flag_,_msg_) \
if (DefaultDebugLevel >= (_level_) && \
DefaultDebugFlags & (_flag_)) { \
DbgPrint ("SMSCIR: "); \
DbgPrint _msg_; \
DbgPrint("\n"); \
}
#endif //WPP_TRACING
//
// Register definitions
//
///////////////////////////////////////////////
// Definitions for Consumer IR RECEIVE block //
///////////////////////////////////////////////
//
// Naster block control available at address 7
// of all register blocks
//
#define CIRCC2_MASTER_BLOCK_CONTROL 7
//
// Register block 0 registers
//
#define CIRCC2_DATA 0
#define CIRCC2_INTERRUPT_ID 1
#define CIRCC2_INTERRUPT_ENABLE 2
#define CIRCC2_LINE_STATUS_R 3
#define CIRCC2_LINE_STATUS_ADDRESS_W 3
#define CIRCC2_LINE_CONTROL_A 4
#define CIRCC2_LINE_CONTROL_B 5
#define CIRCC2_BUS_STATUS 6
//
// Register block 1 registers
//
#define CIRCC2_SCE_CONFIG_A 0
#define CIRCC2_SCE_CONFIG_B 1
#define CIRCC2_FIFO_THRESHOLD 2
#define CIRCC2_FIFO_COUNT 3
#define CIRCC2_MSG_BYTE_COUNT_LOW 4
#define CIRCC2_MSG_BYTE_COUNT_HIGH 5
#define CIRCC2_SCE_CONFIG_C 6
//
// Register block 2 registers
//
#define CIRCC2_CONSUMER_IR_CTRL 0
#define CIRCC2_CONSUMER_IR_CARRIER 1
#define CIRCC2_CONSUMER_IR_BIT_RATE 2
#define CIRCC2_CUSTOM_CODE 3
#define CIRCC2_CUSTOM_CODE_PRIME 4
#define CIRCC2_DATA_CODE 5
#define CIRCC2_CONSUMER_PROTOCOL_SELECT 6
//
// Register block 3 registers
//
#define CIRCC2_SMSC_ID_HIGH 0
#define CIRCC2_SMSC_ID_LOW 1
#define CIRCC2_CHIP_ID 2
#define CIRCC2_VERSION_NUMBER 3
#define CIRCC2_IRQ_LEVEL_DMA_CHANNEL 4
#define CIRCC2_SOFTWARE_SELECT_A 5
//
// Software Select A is also a special "was system
// woken by remote" BOOLEAN register. If the
// device was used to wake the system, this register
// will have a value of 1, 0 otherwise.
//
#define CIRCC2_WAS_REMOTE_WAKE 5
#define CIRCC2_SOFTWARE_SELECT_B 6
//
// Register block 4 registers
//
#define CIRCC2_RX_DATA_SIZE_HIGH 5
#define CIRCC2_RX_DATA_SIZE_LOW 6
//
// Register block 5 registers
//
#define CIRCC2_HALF_DUPLEX_TIMEOUT 1
#define CIRCC2_SCE_TRANSMIT_DELAY_TIMER 2
#define CIRCC2_CARRIER_CAPTURE_CONTROL 3
#define CIRCC2_CARRIER_CAPTURE_MEASURE 4
//
// Register block 6 registers
//
#define CIRCC2_HEADER_VALUE_AND_MASK 0
#define CIRCC2_DATA_VALUE_1 1
#define CIRCC2_DATA_MASK_1 2
#define CIRCC2_DATA_VALUE_2 3
#define CIRCC2_DATA_MASK_2 4
#define CIRCC2_DATA_VALUE_3 5
#define CIRCC2_DATA_MASK_3 6
//
// Register block 7 registers
//
#define CIRCC2_DATA_VALUE_4 0
#define CIRCC2_DATA_MASK_4 1
#define CIRCC2_DATA_VALUE_5 2
#define CIRCC2_DATA_MASK_5 3
#define CIRCC2_DOWN_COUNTER_CONTROL 5
#define CIRCC2_DOWN_COUNTER 6
//
// Structure definitions to match registers of interest
//
#include <pshpack1.h>
//
// CIRCC2_MASTER_BLOCK_CONTROL
//
typedef struct _MASTER_BLOCK_CONTROL {
union {
struct {
UCHAR RegisterBlockSelect : 3;
UCHAR Reserved : 1;
UCHAR ErrorReset : 1;
UCHAR MasterInterruptEnable : 1;
UCHAR MasterReset : 1;
UCHAR PowerDown : 1;
};
UCHAR AsUChar;
};
}MASTER_BLOCK_CONTROL, *PMASTER_BLOCK_CONTROL;
//
// CIRCC2_INTERRUPT_ID
// CIRCC2_INTERRUPT_ENABLE
//
typedef struct _INTERRUPT_ID_OR_ENABLE {
union {
struct {
UCHAR Reserved : 1;
UCHAR CarrierCapture : 1;
UCHAR GpCp : 1;
UCHAR IrBusy : 1;
UCHAR Fifo : 1;
UCHAR RawMode : 1;
UCHAR Eom : 1;
UCHAR ActiveFrame : 1;
};
UCHAR AsUChar;
};
}INTERRUPT_ID_OR_ENABLE, *PINTERRUPT_ID_OR_ENABLE;
//
// CIRCC2_LINE_STATUS_R
//
typedef struct _LINE_STATUS_READ {
union {
struct {
UCHAR NECRepeat : 1;
UCHAR Reserved : 1;
UCHAR FrameAbort : 1;
UCHAR CRCError : 1;
UCHAR SizeError : 1;
UCHAR FrameError : 1;
UCHAR OverRun : 1;
UCHAR UnderRun : 1;
};
UCHAR AsUChar;
};
}LINE_STATUS_READ, *PLINE_STATUS_READ;
//
// CIRCC2_LINE_STATUS_ADDRESS_W
//
typedef struct _LINE_STATUS_ADDRESS_WRITE {
union {
struct {
UCHAR StatusRegisterAddress : 3;
UCHAR Reserved : 5;
};
UCHAR AsUChar;
};
}LINE_STATUS_ADDRESS_WRITE, *PLINE_STATUS_ADDRESS_WRITE;
//
// CIRCC2_LINE_CONTROL_A
//
typedef struct _LINE_CONTROL_A {
union {
struct {
UCHAR Reserved0 : 3;
UCHAR RawRx : 1;
UCHAR RawTx : 1;
UCHAR Reserved1 : 2;
UCHAR FifoReset : 1;
};
UCHAR AsUChar;
};
}LINE_CONTROL_A, *PLINE_CONTROL_A;
//
// CIRCC2_LINE_CONTROL_B
//
typedef struct _LINE_CONTROL_B {
union {
struct {
UCHAR MessageCount : 4;
UCHAR Reserved : 2;
UCHAR SCEModeBits : 2;
};
UCHAR AsUChar;
};
}LINE_CONTROL_B, *PLINE_CONTROL_B;
#define SCE_MODE_TRANSMIT 1
#define SCE_MODE_RECEIVE 2
//
// CIRCC2_BUS_STATUS
//
typedef struct _BUS_STATUS {
union {
struct {
UCHAR ValidFrame : 1;
UCHAR Reserved : 4;
UCHAR Timeout : 1;
UCHAR FifoFull : 1;
UCHAR NotEmpty : 1;
};
UCHAR AsUChar;
};
}BUS_STATUS, *PBUS_STATUS;
//
// CIRCC2_SCE_CONFIG_A
//
typedef struct _SCE_CONFIG_A {
union {
struct {
UCHAR RxPolarity : 1;
UCHAR TxPolarity : 1;
UCHAR HalfDuplex : 1;
UCHAR BlockControl : 4;
UCHAR AuxIr : 1;
};
UCHAR AsUChar;
};
}SCE_CONFIG_A, *PSCE_CONFIG_A;
//
// CIRCC2_SCE_CONFIG_B
//
typedef struct _SCE_CONFIG_B {
union {
struct {
UCHAR DmaEnable : 1;
UCHAR DmaBurst : 1;
UCHAR StringMove : 1;
UCHAR NoWait : 1;
UCHAR LoopBack : 2;
UCHAR OutputMux : 2;
};
UCHAR AsUChar;
};
}SCE_CONFIG_B, *PSCE_CONFIG_B;
#define SCE_CONFIB_B_NORMAL_MUX 1
#define SCE_CONFIB_B_LEARN_MUX 2
//
// CIRCC2_SCE_CONFIG_C
//
typedef struct _SCE_CONFIG_C {
union {
struct {
UCHAR DmaRefreshCount : 2;
UCHAR Reserved : 4;
UCHAR TxPulseWidthLimit : 1;
UCHAR Reserved2 : 1;
};
UCHAR AsUChar;
};
}SCE_CONFIG_C, *PSCE_CONFIG_C;
//
// CIRCC2_CONSUMER_IR_CTRL
//
typedef struct _CONSUMER_IR_CTRL {
union {
struct {
UCHAR CarrierRange : 2;
UCHAR CarrierOff : 1;
UCHAR NoCareDataCode : 1;
UCHAR NoCareCustomCode : 1;
UCHAR PMEWake : 1;
UCHAR Frame : 1;
UCHAR ReceiveSync : 1;
};
UCHAR AsUChar;
};
}CONSUMER_IR_CTRL, *PCONSUMER_IR_CTRL;
//
// CIRCC2_CONSUMER_PROTOCOL_SELECT
//
typedef struct _CONSUMER_PROTOCOL_SELECT {
union {
struct {
UCHAR FrameType : 3;
UCHAR Reserved : 2;
UCHAR SingleByteCCode : 2;
UCHAR RxNECRepeated : 1;
};
UCHAR AsUChar;
};
}CONSUMER_PROTOCOL_SELECT, *PCONSUMER_PROTOCOL_SELECT;
//
// CIRCC2_CARRIER_CAPTURE_CONTROL
//
typedef struct _CARRIER_CAPTURE_CONTROL {
union {
struct {
UCHAR CaptureMeasurement : 1;
UCHAR CaptureReset : 1;
UCHAR Reserved : 6;
};
UCHAR AsUChar;
};
}CARRIER_CAPTURE_CONTROL, *PCARRIER_CAPTURE_CONTROL;
////////////////////////////////////////////////
// Definitions for Consumer IR BLASTING block //
////////////////////////////////////////////////
//
// Naster block control available at address 7
// of all register blocks
//
#define BIRCC2_MASTER_BLOCK_CONTROL_ADDR 7
//
// Register block 0 registers
//
#define BIRCC2_DATA_ADDR 0
#define BIRCC2_INTERRUPT_ID_ADDR 1
#define BIRCC2_INTERRUPT_ENABLE_ADDR 2
#define BIRCC2_LINE_CONTROL_ADDR 3
#define BIRCC2_DOWN_COUNTER_CONTROL_ADDR 4
#define BIRCC2_DOWN_COUNTER_ADDR 5
#define BIRCC2_TX_CHANNEL_ENABLES_ADDR 6
//
// Register block 1 registers
//
#define BIRCC2_MODE_ADDR 0
#define BIRCC2_CONSUMER_IR_CARRIER 1
#define BIRCC2_CONSUMER_IR_BIT_RATE 2
#define BIRCC2_FIFO_THRESHOLD_ADDR 3
#define BIRCC2_FIFO_COUNT_ADDR 4
#define BIRCC2_TX_DELAY_TIMER_ADDR 5
//
// Register block 2 registers
//
#define BIRCC2_SMSC_ID_HIGH_ADDR 0
#define BIRCC2_SMSC_ID_LOW_ADDR 1
#define BIRCC2_BLOCK_ID_ADDR 2
#define BIRCC2_VERSION_ADDR 3
#define BIRCC2_BLOCK_CONFIG_ADDR 4
#define BIRCC2_SOFTWARE_SELECT_A_ADDR 5
#define BIRCC2_SOFTWARE_SELECT_B_ADDR 6
//
// BIRCC2_MASTER_BLOCK_CONTROL_ADDR
//
typedef struct _BIRCC2_MASTER_BLOCK_CONTROL {
union {
struct {
UCHAR RegisterBlockSelect : 2;
UCHAR Reserved : 3;
UCHAR MasterInterruptEnable : 1;
UCHAR MasterReset : 1;
UCHAR PowerDown : 1;
};
UCHAR AsUChar;
};
}BIRCC2_MASTER_BLOCK_CONTROL, *PBIRCC2_MASTER_BLOCK_CONTROL;
//
// BIRCC2_INTERRUPT_ID_ADDR
// BIRCC2_INTERRUPT_ENABLE_ADDR
//
typedef struct _BIRCC2_INTERRUPT_ID_OR_ENABLE {
union {
struct {
UCHAR Reserved : 4;
UCHAR DownCounter : 1;
UCHAR TxActivated : 1;
UCHAR TxComplete : 1;
UCHAR Fifo : 1;
};
UCHAR AsUChar;
};
}BIRCC2_INTERRUPT_ID_OR_ENABLE, *PBIRCC2_INTERRUPT_ID_OR_ENABLE;
//
// BIRCC2_LINE_CONTROL_ADDR
//
typedef struct _BIRCC2_LINE_CONTROL {
union {
struct {
UCHAR TxEnable : 1;
UCHAR RawTx : 1;
UCHAR Reserved : 2;
UCHAR TxActive : 1;
UCHAR FifoReset : 1;
UCHAR FifoNotEmpty : 1;
UCHAR FifoFull : 1;
};
UCHAR AsUChar;
};
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