📄 mxl5005_c.c
字号:
{
status += MXL_ControlWrite(Tuner, CHCAL_EN_INT_RF, 0);
}
//if (E5 == 0)
// status += MXL_ControlWrite(Tuner, CHCAL_EN_INT_RF, 1);
//else
// status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, E5) ;
//
// Set TG Synth
//
// Look-Up table implementation for:
// TG_LO_DIVVAL
// TG_LO_SELVAL
//
// Set divider_val, Fmax, Fmix to use in Equations
if (Tuner->TG_LO < 33000000UL) {
return -1;
}
FminBin = 33000000UL ;
FmaxBin = 50000000UL ;
if (Tuner->TG_LO >= FminBin && Tuner->TG_LO <= FmaxBin) {
status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x6) ;
status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x0) ;
divider_val = 36 ;
Fmax = FmaxBin ;
Fmin = FminBin ;
}
FminBin = 50000000UL ;
FmaxBin = 67000000UL ;
if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) {
status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x1) ;
status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x0) ;
divider_val = 24 ;
Fmax = FmaxBin ;
Fmin = FminBin ;
}
FminBin = 67000000UL ;
FmaxBin = 100000000UL ;
if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) {
status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0xC) ;
status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x2) ;
divider_val = 18 ;
Fmax = FmaxBin ;
Fmin = FminBin ;
}
FminBin = 100000000UL ;
FmaxBin = 150000000UL ;
if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) {
status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x8) ;
status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x2) ;
divider_val = 12 ;
Fmax = FmaxBin ;
Fmin = FminBin ;
}
FminBin = 150000000UL ;
FmaxBin = 200000000UL ;
if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) {
status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x0) ;
status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x2) ;
divider_val = 8 ;
Fmax = FmaxBin ;
Fmin = FminBin ;
}
FminBin = 200000000UL ;
FmaxBin = 300000000UL ;
if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) {
status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x8) ;
status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x3) ;
divider_val = 6 ;
Fmax = FmaxBin ;
Fmin = FminBin ;
}
FminBin = 300000000UL ;
FmaxBin = 400000000UL ;
if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) {
status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x0) ;
status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x3) ;
divider_val = 4 ;
Fmax = FmaxBin ;
Fmin = FminBin ;
}
FminBin = 400000000UL ;
FmaxBin = 600000000UL ;
if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) {
status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x8) ;
status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x7) ;
divider_val = 3 ;
Fmax = FmaxBin ;
Fmin = FminBin ;
}
FminBin = 600000000UL ;
FmaxBin = 900000000UL ;
if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) {
status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x0) ;
status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x7) ;
divider_val = 2 ;
Fmax = FmaxBin ;
Fmin = FminBin ;
}
// TG_DIV_VAL
tg_divval = (Tuner->TG_LO*divider_val/100000)
*(MXL_Ceiling(Tuner->Fxtal,1000000) * 100) / (Tuner->Fxtal/1000) ;
status += MXL_ControlWrite(Tuner, TG_DIV_VAL, tg_divval) ;
if (Tuner->TG_LO > 600000000UL)
status += MXL_ControlWrite(Tuner, TG_DIV_VAL, tg_divval + 1 ) ;
Fmax = 1800000000UL ;
Fmin = 1200000000UL ;
// to prevent overflow of 32 bit unsigned integer, use following equation. Edit for v2.6.4
Fref_TG = (Tuner->Fxtal/1000)/ MXL_Ceiling(Tuner->Fxtal, 1000000) ; // Fref_TF = Fref_TG*1000
Fvco = (Tuner->TG_LO/10000) * divider_val * Fref_TG; //Fvco = Fvco/10
tg_lo = (((Fmax/10 - Fvco)/100)*32) / ((Fmax-Fmin)/1000)+8;
//below equation is same as above but much harder to debug.
//tg_lo = ( ((Fmax/10000 * Xtal_Int)/100) - ((Tuner->TG_LO/10000)*divider_val*(Tuner->Fxtal/10000)/100) )*32/((Fmax-Fmin)/10000 * Xtal_Int/100) + 8 ;
status += MXL_ControlWrite(Tuner, TG_VCO_BIAS , tg_lo) ;
//add for 2.6.5
//Special setting for QAM
if(Tuner ->Mod_Type == MXL_QAM)
{
if(Tuner->RF_IN < 680000000)
status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 3) ;
else
status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 2) ;
}
//remove 20.48MHz setting for 2.6.10
//
// Off Chip Tracking Filter Control
//
if (Tuner->TF_Type == MXL_TF_OFF) // Tracking Filter Off State; turn off all the banks
{
status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ;
status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ;
status += MXL_SetGPIO(Tuner, 3, 1) ; // turn off Bank 1
status += MXL_SetGPIO(Tuner, 1, 1) ; // turn off Bank 2
status += MXL_SetGPIO(Tuner, 4, 1) ; // turn off Bank 3
}
if (Tuner->TF_Type == MXL_TF_C) // Tracking Filter type C
{
status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ;
status += MXL_ControlWrite(Tuner, DAC_DIN_A, 0) ;
if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 150000000)
{
status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off
status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ;
status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank1 On
status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank3 Off
}
if (Tuner->RF_IN >= 150000000 && Tuner->RF_IN < 280000000)
{
status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off
status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ;
status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off
status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On
status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank3 Off
}
if (Tuner->RF_IN >= 280000000 && Tuner->RF_IN < 360000000)
{
status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off
status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ;
status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off
status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On
status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank3 On
}
if (Tuner->RF_IN >= 360000000 && Tuner->RF_IN < 560000000)
{
status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off
status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ;
status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off
status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank3 On
}
if (Tuner->RF_IN >= 560000000 && Tuner->RF_IN < 580000000)
{
status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On
status += MXL_ControlWrite(Tuner, DAC_DIN_B, 29) ;
status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off
status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank3 On
}
if (Tuner->RF_IN >= 580000000 && Tuner->RF_IN < 630000000)
{
status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On
status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ;
status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off
status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank3 On
}
if (Tuner->RF_IN >= 630000000 && Tuner->RF_IN < 700000000)
{
status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On
status += MXL_ControlWrite(Tuner, DAC_DIN_B, 16) ;
status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off
status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank3 Off
}
if (Tuner->RF_IN >= 700000000 && Tuner->RF_IN < 760000000)
{
status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On
status += MXL_ControlWrite(Tuner, DAC_DIN_B, 7) ;
status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off
status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank3 Off
}
if (Tuner->RF_IN >= 760000000 && Tuner->RF_IN <= 900000000)
{
status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On
status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ;
status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off
status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank3 Off
}
}
if (Tuner->TF_Type == MXL_TF_C_H) // Tracking Filter type C-H for Hauppauge only
{
status += MXL_ControlWrite(Tuner, DAC_DIN_A, 0) ;
if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 150000000)
{
status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off
status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On
status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off
status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank3 Off
}
if (Tuner->RF_IN >= 150000000 && Tuner->RF_IN < 280000000)
{
status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off
status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank2 On
status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank3 Off
}
if (Tuner->RF_IN >= 280000000 && Tuner->RF_IN < 360000000)
{
status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off
status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank2 On
status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank3 On
}
if (Tuner->RF_IN >= 360000000 && Tuner->RF_IN < 560000000)
{
status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off
status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off
status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank3 On
}
if (Tuner->RF_IN >= 560000000 && Tuner->RF_IN < 580000000)
{
status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On
status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off
status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank3 On
}
if (Tuner->RF_IN >= 580000000 && Tuner->RF_IN < 630000000)
{
status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On
status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off
status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank3 On
}
if (Tuner->RF_IN >= 630000000 && Tuner->RF_IN < 700000000)
{
status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On
status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off
status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank3 Off
}
if (Tuner->RF_IN >= 700000000 && Tuner->RF_IN < 760000000)
{
status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On
status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off
status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank3 Off
}
if (Tuner->RF_IN >= 760000000 && Tuner->RF_IN <= 900000000)
{
status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On
status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off
status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank3 Off
}
}
if (Tuner->TF_Type == MXL_TF_D) // Tracking Filter type D
{
status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ;
if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 174000000)
{
status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off
status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On
status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off
}
if (Tuner->RF_IN >= 174000000 && Tuner->RF_IN < 250000000)
{
status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off
status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On
status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On
status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off
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