📄 mxl5005_c.c
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//
// Downconverter Controls
//
// Look-Up Table Implementation for:
// DN_POLY
// DN_RFGAIN
// DN_CAP_RFLPF
// DN_EN_VHFUHFBAR
// DN_GAIN_ADJUST
// Change the boundary reference from RF_IN to RF_LO
if (Tuner->RF_LO < 40000000UL) {
return -1;
}
if (Tuner->RF_LO >= 40000000UL && Tuner->RF_LO <= 75000000UL) {
// Look-Up Table implementation
status += MXL_ControlWrite(Tuner, DN_POLY, 2) ;
status += MXL_ControlWrite(Tuner, DN_RFGAIN, 3) ;
status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 423) ;
status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 1) ;
status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 1) ;
}
if (Tuner->RF_LO > 75000000UL && Tuner->RF_LO <= 100000000UL) {
// Look-Up Table implementation
status += MXL_ControlWrite(Tuner, DN_POLY, 3) ;
status += MXL_ControlWrite(Tuner, DN_RFGAIN, 3) ;
status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 222) ;
status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 1) ;
status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 1) ;
}
if (Tuner->RF_LO > 100000000UL && Tuner->RF_LO <= 150000000UL) {
// Look-Up Table implementation
status += MXL_ControlWrite(Tuner, DN_POLY, 3) ;
status += MXL_ControlWrite(Tuner, DN_RFGAIN, 3) ;
status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 147) ;
status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 1) ;
status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 2) ;
}
if (Tuner->RF_LO > 150000000UL && Tuner->RF_LO <= 200000000UL) {
// Look-Up Table implementation
status += MXL_ControlWrite(Tuner, DN_POLY, 3) ;
status += MXL_ControlWrite(Tuner, DN_RFGAIN, 3) ;
status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 9) ;
status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 1) ;
status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 2) ;
}
if (Tuner->RF_LO > 200000000UL && Tuner->RF_LO <= 300000000UL) {
// Look-Up Table implementation
status += MXL_ControlWrite(Tuner, DN_POLY, 3) ;
status += MXL_ControlWrite(Tuner, DN_RFGAIN, 3) ;
status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 0) ;
status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 1) ;
status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 3) ;
}
if (Tuner->RF_LO > 300000000UL && Tuner->RF_LO <= 650000000UL) {
// Look-Up Table implementation
status += MXL_ControlWrite(Tuner, DN_POLY, 3) ;
status += MXL_ControlWrite(Tuner, DN_RFGAIN, 1) ;
status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 0) ;
status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 0) ;
status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 3) ;
}
if (Tuner->RF_LO > 650000000UL && Tuner->RF_LO <= 900000000UL) {
// Look-Up Table implementation
status += MXL_ControlWrite(Tuner, DN_POLY, 3) ;
status += MXL_ControlWrite(Tuner, DN_RFGAIN, 2) ;
status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 0) ;
status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 0) ;
status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 3) ;
}
if (Tuner->RF_LO > 900000000UL) {
return -1;
}
// DN_IQTNBUF_AMP
// DN_IQTNGNBFBIAS_BST
if (Tuner->RF_LO >= 40000000UL && Tuner->RF_LO <= 75000000UL) {
status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ;
status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ;
}
if (Tuner->RF_LO > 75000000UL && Tuner->RF_LO <= 100000000UL) {
status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ;
status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ;
}
if (Tuner->RF_LO > 100000000UL && Tuner->RF_LO <= 150000000UL) {
status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ;
status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ;
}
if (Tuner->RF_LO > 150000000UL && Tuner->RF_LO <= 200000000UL) {
status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ;
status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ;
}
if (Tuner->RF_LO > 200000000UL && Tuner->RF_LO <= 300000000UL) {
status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ;
status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ;
}
if (Tuner->RF_LO > 300000000UL && Tuner->RF_LO <= 400000000UL) {
status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ;
status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ;
}
if (Tuner->RF_LO > 400000000UL && Tuner->RF_LO <= 450000000UL) {
status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ;
status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ;
}
if (Tuner->RF_LO > 450000000UL && Tuner->RF_LO <= 500000000UL) {
status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ;
status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ;
}
if (Tuner->RF_LO > 500000000UL && Tuner->RF_LO <= 550000000UL) {
status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ;
status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ;
}
if (Tuner->RF_LO > 550000000UL && Tuner->RF_LO <= 600000000UL) {
status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ;
status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ;
}
if (Tuner->RF_LO > 600000000UL && Tuner->RF_LO <= 650000000UL) {
status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ;
status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ;
}
if (Tuner->RF_LO > 650000000UL && Tuner->RF_LO <= 700000000UL) {
status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ;
status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ;
}
if (Tuner->RF_LO > 700000000UL && Tuner->RF_LO <= 750000000UL) {
status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ;
status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ;
}
if (Tuner->RF_LO > 750000000UL && Tuner->RF_LO <= 800000000UL) {
status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ;
status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ;
}
if (Tuner->RF_LO > 800000000UL && Tuner->RF_LO <= 850000000UL) {
status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 10) ;
status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 1) ;
}
if (Tuner->RF_LO > 850000000UL && Tuner->RF_LO <= 900000000UL) {
status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 10) ;
status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 1) ;
}
//
// Set RF Synth and LO Path Control
//
// Look-Up table implementation for:
// RFSYN_EN_OUTMUX
// RFSYN_SEL_VCO_OUT
// RFSYN_SEL_VCO_HI
// RFSYN_SEL_DIVM
// RFSYN_RF_DIV_BIAS
// DN_SEL_FREQ
//
// Set divider_val, Fmax, Fmix to use in Equations
FminBin = 28000000UL ;
FmaxBin = 42500000UL ;
if (Tuner->RF_LO >= 40000000UL && Tuner->RF_LO <= FmaxBin) {
status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 1) ;
status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 0) ;
status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0) ;
status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ;
status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ;
status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 1) ;
divider_val = 64 ;
Fmax = FmaxBin ;
Fmin = FminBin ;
}
FminBin = 42500000UL ;
FmaxBin = 56000000UL ;
if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) {
status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 1) ;
status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 0) ;
status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1) ;
status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ;
status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ;
status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 1) ;
divider_val = 64 ;
Fmax = FmaxBin ;
Fmin = FminBin ;
}
FminBin = 56000000UL ;
FmaxBin = 85000000UL ;
if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) {
status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ;
status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ;
status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0) ;
status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ;
status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ;
status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 1) ;
divider_val = 32 ;
Fmax = FmaxBin ;
Fmin = FminBin ;
}
FminBin = 85000000UL ;
FmaxBin = 112000000UL ;
if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) {
status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ;
status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ;
status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1) ;
status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ;
status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ;
status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 1) ;
divider_val = 32 ;
Fmax = FmaxBin ;
Fmin = FminBin ;
}
FminBin = 112000000UL ;
FmaxBin = 170000000UL ;
if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) {
status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ;
status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ;
status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0) ;
status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ;
status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ;
status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 2) ;
divider_val = 16 ;
Fmax = FmaxBin ;
Fmin = FminBin ;
}
FminBin = 170000000UL ;
FmaxBin = 225000000UL ;
if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) {
status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ;
status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ;
status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1) ;
status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ;
status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ;
status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 2) ;
divider_val = 16 ;
Fmax = FmaxBin ;
Fmin = FminBin ;
}
FminBin = 225000000UL ;
FmaxBin = 300000000UL ;
if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) {
status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ;
status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ;
status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0) ;
status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ;
status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ;
status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 4) ;
divider_val = 8 ;
Fmax = 340000000UL ;
Fmin = FminBin ;
}
FminBin = 300000000UL ;
FmaxBin = 340000000UL ;
if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) {
status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 1) ;
status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 0) ;
status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0) ;
status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ;
status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ;
status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0) ;
divider_val = 8 ;
Fmax = FmaxBin ;
Fmin = 225000000UL ;
}
FminBin = 340000000UL ;
FmaxBin = 450000000UL ;
if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) {
status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 1) ;
status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 0) ;
status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1) ;
status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ;
status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 2) ;
status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0) ;
divider_val = 8 ;
Fmax = FmaxBin ;
Fmin = FminBin ;
}
FminBin = 450000000UL ;
FmaxBin = 680000000UL ;
if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) {
status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ;
status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ;
status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0) ;
status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 1) ;
status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ;
status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0) ;
divider_val = 4 ;
Fmax = FmaxBin ;
Fmin = FminBin ;
}
FminBin = 680000000UL ;
FmaxBin = 900000000UL ;
if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) {
status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ;
status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ;
status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1) ;
status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 1) ;
status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ;
status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0) ;
divider_val = 4 ;
Fmax = FmaxBin ;
Fmin = FminBin ;
}
// CHCAL_INT_MOD_RF
// CHCAL_FRAC_MOD_RF
// RFSYN_LPF_R
// CHCAL_EN_INT_RF
// Equation E3
// RFSYN_VCO_BIAS
E3 = (((Fmax-Tuner->RF_LO)/1000)*32)/((Fmax-Fmin)/1000) + 8 ;
status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, E3) ;
// Equation E4
// CHCAL_INT_MOD_RF
E4 = (Tuner->RF_LO*divider_val/1000)/(2*Tuner->Fxtal*Kdbl_RF/1000) ;
MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, E4) ;
// Equation E5
// CHCAL_FRAC_MOD_RF
// CHCAL_EN_INT_RF
E5 = ((2<<17)*(Tuner->RF_LO/10000*divider_val - (E4*(2*Tuner->Fxtal*Kdbl_RF)/10000)))/(2*Tuner->Fxtal*Kdbl_RF/10000) ;
status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, E5) ;
// Equation E5A
// RFSYN_LPF_R
E5A = (((Fmax - Tuner->RF_LO)/1000)*4/((Fmax-Fmin)/1000)) + 1 ;
status += MXL_ControlWrite(Tuner, RFSYN_LPF_R, E5A) ;
// Euqation E5B
// CHCAL_EN_INIT_RF
if (E5 == 0)
{
status += MXL_ControlWrite(Tuner, CHCAL_EN_INT_RF, 1);
}
else
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