ct_nim.c
来自「DVB软件,基于CT216软件的开发源程序.」· C语言 代码 · 共 1,736 行 · 第 1/3 页
C
1,736 行
Status = CT221_Read_ICFO();
if((Status != TRUE) && (count > 30))
{
CTNIM_MSG(("Check ICFO TimeOut\n"));
return DRVERR_NOTOK;
}
else if (Status == TRUE)
{
if(CT221_Lock_Status())
{
return DRV_OK;
}
}
if(u16Mode == CT_NIM_CHANNEL_MODE_SCAN)
{
CT_OS_GetClock(&u32Current_Timer_Tick); // Get current time ticks
if ( CT_OS_TimerAfter( u32Current_Timer_Tick, u32TimeOutTick )==TRUE ) // Check time out
{
CTNIM_MSG(("TimeOut\n"));
break;
}
}
else
{
CT_OS_GetClock(&u32Current_Timer_Tick); // Get current time ticks
if ( CT_OS_TimerAfter( u32Current_Timer_Tick, u32TimeOutTick )==TRUE ) // Check time out
{
CTNIM_MSG(("TimeOut\n"));
break;
}
}
//*
if ( CT_OS_Delay(1)!=EN_CTOS_SUCCESS )
{
return DRVERR_NOTOK;
}
//*/
}
CTNIM_MSG(("TimeOut\n"));
return DRVERR_NOTOK; //Timeout
}
EN_DRV_RESULT CT_NIM_Monitor(FN_NIM_EVENT_NOTIFY EventHandle)
{
//static bool8 b8Status = FALSE;
static u8 u8count = 0;
//static u8 u8CLOFCount = 0;
static u32 SNR_ref=0;
static u32 SNR_cur[5] = {0,0,0,0,0};
static bool8 b8FirstUpdate_SNR = TRUE;
u32 tmp,sum, i;
bool8 b8tmp;
#ifdef CT_OS_CHECK_STACKSIZE
CT_OS_RecordTaskStack();
#endif
#ifdef CT_NIM_VOID
if(b8NIMDebugMode)
{
return DRV_OK;
}
#endif
// return DRV_OK;
if ( CT221_GetState()!=EN_CT221_STATE_READY )
{
return DRV_OK;
}
/* //for NXP N+1 ACI
#if (TUNER_TYPE == TUNER_TD1611)
CT221_AGC_Target(FALSE);
#endif
*/
if(Tuner_Init.enCCILoop1 == EN_MONITORCCI1_ON)//#if defined MONITORCCI1 //MONITORCCI-1
{
if (u8chswitch > 0)
{
if((CT221_TPS_Lock_Status() == TRUE))
{
printf("CCI loop1\n");
if (CT221_Set_CCI_First(u32OffSetFreq) == TRUE)
{
u8chswitch = 0;
CT221_Reset_DAGCtarget(FALSE);
}
else
{
CT_OS_MS_Delay(50);
if (CT221_Set_CCI_First(u32OffSetFreq) == TRUE)
{
u8chswitch = 0;
CT221_Reset_DAGCtarget(FALSE);
}
else
{
u8chswitch++;
}
}
if (u8chswitch >= 2)
{
u8chswitch = 0;
CT221_Reset_DAGCtarget(TRUE);
}
}
}
}
else//#else
{
u8chswitch = 0;
}//#endif
#if 1 //MONITORCCI-2
if(u8chswitch == 0)
{
#if 1 //old cci loop 2
// software CCI detection
if (CT221_Get_SD_TRK_Status() == TRUE)
{// wait for SD stable and than start the software CCI detection
CT221_Set_CCI_Detection();
}
// ==> Start of the SDA reset checking.
if((CT221_Lock_Status() == TRUE) )
{
//CT221_Monitor_CPE();//Kelvin, add, 2008/04/19, Disable by KS 2008/07/18
if (b8FirstUpdate_SNR==TRUE)
{
u8SDRstCnt = 0;
SNR_cur[0] = CT221_Get_SNR();
for (i = 1; i<5;i++)
{
SNR_cur[i] = CT221_Get_SNR();
if (abs(SNR_cur[i] - SNR_cur[i-1]) < 100)
{
u8SDRstCnt++;
}
}
if (u8SDRstCnt>=4)
{
CTNIM_DBG(("First Update SNR_ref\n"));
sum = 0;
for (i=0;i<5;i++)
{
sum += SNR_cur[i];
}
SNR_ref = sum/5;
b8FirstUpdate_SNR = FALSE;
}
}
else /* Monitor SNR and update current SNR if needed */
{
/*CTNIM_DBG(("SNR Loop!!!!!\n"));*/
u8SDRstCnt = 0;
for (i = 0; i< 5;i++)
{
SNR_cur[i] = CT221_Get_SNR();
/*printf ("Current SNR is %f\n", SNR_cur); */
b8tmp = CT221_Get_CCI_Detection();
tmp = abs(SNR_cur[i] - SNR_ref);
//printf ("SNR_ref = %d, SNR_cur = %d\n", SNR_ref, SNR_cur);
if ((tmp > 100) && b8tmp )
{
u8SDRstCnt++ ;
}
/*printf ("%d, |SNR_cur - SNR_ref| = %d, CCT_det = %d\n",i, tmp, b8tmp);*/
}
/*CTNIM_DBG(("u8SDRstCnt = %d\n", u8SDRstCnt));*/
if (u8SDRstCnt >=5)
{
//printf ("SDA Reset!\n");
/*printf ("|SNR_cur - SNR_ref| = %d, CCT_det = %d", tmp, b8tmp);*/
CT221_ResetSDA();
sum = 0;
for (i=0;i<5;i++)
{
sum += SNR_cur[i];
}
SNR_ref = sum/5;
/*b8FirstUpdate_SNR = TRUE;*/
}
}
}// <<= End of the SDA reset checking.
/*else//if((CT221_Lock_Status() == TRUE))
{
//for freqency offset recompense
if(u8CLOFCount == 20)
{
CT221_CheckLOFreq();
}
if(u8CLOFCount > 20)
{
if( (u16TempBW == 7) && (CT221_CheckLOFreq() == TRUE))
{
CT221_WriteReg(0x14, 0x00); // stop Hw resync
CT221_LO_Freq_Conv(FFT_8KMODE, u16TempBW);
CT221_SetType(TYPE_NORMAL); // stop Hw resync
u8CLOFCount = 0;
}
}
u8CLOFCount++;
}
//*/
#else //new cci loop 2
// software CCI detection
if (CT221_Get_SD_TRK_Status() == TRUE)
{// wait for SD stable and than start the software CCI detection
if( CT221_Set_CCI_Detection() == TRUE)
{
u8SDRstCnt = 0;
}
}
// ==> Start of the SDA reset checking.
if((CT221_Lock_Status() == TRUE) )
{
//CT221_Monitor_CPE();//Kelvin, add, 2008/04/19, Disable by KS 2008/07/18
if (b8FirstUpdate_SNR==TRUE)
{
u8SDRstCnt = 0;
SNR_cur[0] = CT221_Get_SNR();
for (i = 1; i<5;i++)
{
SNR_cur[i] = CT221_Get_SNR();
if (abs(SNR_cur[i] - SNR_cur[i-1]) < 100)
{
u8SDRstCnt++;
}
}
if (u8SDRstCnt>=4)
{
CTNIM_DBG(("First Update SNR_ref\n"));
sum = 0;
for (i=0;i<5;i++)
{
sum += SNR_cur[i];
}
SNR_ref = sum/5;
b8FirstUpdate_SNR = FALSE;
u8SDRstCnt = 0;
}
}
else /* Monitor SNR and update current SNR if needed */
{
/*CTNIM_DBG(("SNR Loop!!!!!\n"));*/
//u8SDRstCnt = 0;
b8tmp = FALSE;
sum = 0;
for (i = 0; i< 5;i++)
{
SNR_cur[i] = CT221_Get_SNR();
/*printf ("Current SNR is %f\n", SNR_cur); */
sum += SNR_cur[i];
b8tmp = CT221_Get_CCI_Detection();
}
sum /= 5;
if(sum > SNR_ref)
tmp = (sum - SNR_ref);
else
tmp = (SNR_ref - sum);
//printf ("SNR_ref = %d, SNR_cur = %d\n", SNR_ref, SNR_cur);
if ((tmp > 300) && b8tmp )
{
u8SDRstCnt++ ;
}
/*printf ("%d, |SNR_cur - SNR_ref| = %d, CCT_det = %d\n",i, tmp, b8tmp);*/
//printf("u8SDRstCnt = %d\n", u8SDRstCnt);
if (u8SDRstCnt >=3)
{
//printf ("CCI2-2 reset SDA Reset!\n");
/*printf ("|SNR_cur - SNR_ref| = %d, CCT_det = %d", tmp, b8tmp);*/
CT221_ResetSDA();
u8SDRstCnt = 0;
/*
sum = 0;
for (i=0;i<5;i++)
{
sum += SNR_cur[i];
}
SNR_ref = sum/5;
*/
SNR_ref = sum;
/*b8FirstUpdate_SNR = TRUE;*/
}
}
}// <<= End of the SDA reset checking.
/*else//if((CT221_Lock_Status() == TRUE))
{
//for freqency offset recompense
if(u8CLOFCount == 20)
{
CT221_CheckLOFreq();
}
if(u8CLOFCount > 20)
{
if( (u16TempBW == 7) && (CT221_CheckLOFreq() == TRUE))
{
CT221_WriteReg(0x14, 0x00); // stop Hw resync
CT221_LO_Freq_Conv(FFT_8KMODE, u16TempBW);
CT221_SetType(TYPE_NORMAL); // stop Hw resync
u8CLOFCount = 0;
}
}
u8CLOFCount++;
}
//*/
#endif //end of new or old cci loop selection
}
#endif //enable/disable cci loop2
if (CT221_GetType() == TYPE_NORMAL)
{
// printf("CT221_Get_Resync()\n");
if (CT221_Get_Resync() == TRUE)
{
//CTNIM_DBG(("\n[#]Monitor Resync"));
// u32TempFreq = 0;
// u16TempBW = 0;
/*
#if (TUNER_TYPE == TUNER_TD1611)
CT221_AGC_Target(TRUE);
CT221_AGC_Target(FALSE);
#endif
*/
u8SDRstCnt = 0; //reset u8SDRstCnt
}
}
if (u8count > 20)
{
CT221_Monitor();
u8count = 0;
}
u8count++;
return DRV_OK;
}
void CT_NIM_SetTSOutput(bool8 b8Enalbe)
{
return;
}
EN_DRV_RESULT CT_NIM_SetAbort(u16 u16Abort)
{
#ifdef CT_OS_CHECK_STACKSIZE
CT_OS_RecordTaskStack();
#endif
if(u16Abort == TRUE)
{
_u16KeyInterrupt = TRUE;
}
else
{
_u16KeyInterrupt = FALSE;
}
return DRV_OK;
}
EN_DRV_RESULT CT_NIM_SetPIO(u16 u16PioBit)
{
#ifdef CT_OS_CHECK_STACKSIZE
CT_OS_RecordTaskStack();
#endif
return DRV_OK;
}
EN_DRV_RESULT CT_NIM_ClearPIO(u16 u16PioBit)
{
#ifdef CT_OS_CHECK_STACKSIZE
CT_OS_RecordTaskStack();
#endif
return DRV_OK;
}
EN_DRV_RESULT CT_NIM_CheckLock(u16* pu16LockStatus)
{
#ifdef CT_OS_CHECK_STACKSIZE
CT_OS_RecordTaskStack();
#endif
#ifdef CT_NIM_VOID
if(b8NIMDebugMode)
{
*pu16LockStatus = TRUE;
return DRV_OK;
}
#endif
if(CT221_Lock_Status() == TRUE) /* current lock status */
{
*pu16LockStatus = TRUE;
//CTNIM_DBG(("\nTRUE"));
// CTNIM_DBG(("\n[END][END][END]"));
}
else
{
*pu16LockStatus = FALSE;
//CTNIM_DBG(("\nFALSE"));
}
return DRV_OK;
}
void CT_NIM_SetBus(EN_CT_NIM_BUS_ID enBusID)
{
stBusID = enBusID;
}
EN_CT_NIM_BUS_ID CT_NIM_GetBus(void)
{
return stBusID;
}
u8* CT_NIM_GetVersion(void)
{
#ifdef CT_OS_CHECK_STACKSIZE
CT_OS_RecordTaskStack();
#endif
return (&Tuner_Init.u8Version[0]);
}
void CT_NIM_Config(EN_CT_DEMUX_DP enDpSel)
{
volatile u32 *vpu32NimCfgReg = (volatile u32 *)(NIM_CFG_BASE);
switch(enDpSel)
{
default:
case DEMUX_DATAPATH_NON:
case DEMUX_DATAPATH_2:
//return DRVERR_NOTSUPPORTED;
break;
case DEMUX_DATAPATH_0:
// config nim 0 only
// assume input is 188 (vld) + 16(no_vld)
*vpu32NimCfgReg |= (1<<6);
*vpu32NimCfgReg &= ~(1<<6); // nim_count => 188
*vpu32NimCfgReg &= ~(1<<4); // will reset wosync state machine
*vpu32NimCfgReg |= (1<<4); // =>wosync
*vpu32NimCfgReg &= ~((0xFF)<<8);
*vpu32NimCfgReg |= ((0x13)<<8);
break;
case DEMUX_DATAPATH_1:
// config nim 1 only
// assume input is 188 (vld) + 16(no_vld)
*vpu32NimCfgReg |= (1<<22);
*vpu32NimCfgReg &= ~(1<<22);// nim_count => 188
*vpu32NimCfgReg &= ~(1<<20);// will reset wosync state machine
*vpu32NimCfgReg |= (1<<20); // =>wosync
*vpu32NimCfgReg &= ~(((u32)(0xFF))<<24);
*vpu32NimCfgReg |= (((u32)(0x13))<<24);
break;
}
}
EN_DRV_RESULT CT_NIM_SetClockInverse(bool8 b8inverse)
{
#ifdef CT_NIM_VOID
if(b8NIMDebugMode)
{
return DRV_OK;
}
#endif
CT221_SetClock(b8inverse);
return DRV_OK;
}
EN_DRV_RESULT CT_NIM_DebugReadReg(u16 u16RegIndex, u16 u16Len)
{
u8 u8Buf, u8index;
if(!u16Len)
u16Len = 1;
else if(u16Len > 0xFF)
u16Len = 0xFF;
for(u8index = u16RegIndex; u8index < u16RegIndex + u16Len; u8index++)
{
CT_NIM_ReadReg(u8index, &u8Buf, 1);
printf("Reg:%02hx, Value:%02hx \n",u8index, u8Buf);
}
return DRV_OK;
}
EN_DRV_RESULT CT_NIM_DebugWriteReg(u16 u16RegIndex, u8 u8Buf)
{
if(CT_NIM_WriteReg(u16RegIndex, &u8Buf, 1) != DRV_OK)
return DRVERR_NOTOK;
else
return DRV_OK;
}
#ifdef CT_NIM_VOID
EN_DRV_RESULT CT_NIM_DebugMode(bool8 b8Switch)
{
if(b8Switch)
b8NIMDebugMode = TRUE;
else
b8NIMDebugMode = FALSE;
}
#endif
EN_DRV_RESULT CT_NIM_SelectTunerType(u8 u8TunerType)
{
switch (u8TunerType)
{
case 0:
CT221_InitValueByTuner(EN_TUNER_DTT74530);
break;
case 1:
CT221_InitValueByTuner(EN_TUNER_LGXX1D);
break;
case 2:
CT221_InitValueByTuner(EN_TUNER_MXL5005);
break;
case 3:
CT221_InitValueByTuner(EN_TUNER_MXL5007);
break;
default:
CT221_InitValueByTuner(DEFAULT_TUNER);
break;
}
return DRV_OK;
}
EN_DRV_RESULT CT_NIM_SelectCountry(u8 u8Country)
{
switch (u8Country)
{
case 0:
CT221_InitValueByCountry(EN_TUNER_COUNTRY_SPAIN);
break;
case 1:
CT221_InitValueByCountry(EN_TUNER_COUNTRY_UK);
break;
case 2:
CT221_InitValueByCountry(EN_TUNER_COUNTRY_EU);
break;
default:
CT221_InitValueByCountry(DEFAULT_COUNTRY);
break;
}
return DRV_OK;
}
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