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VTX 2121, 0, 0
{
COORD (460,800)
}
VTX 2122, 0, 0
{
COORD (620,800)
}
BUS 2123, 0, 0
{
NET 2116
VTX 2121, 2122
VARIABLES
{
#NAMED="1"
}
}
VTX 2124, 0, 0
{
COORD (460,1160)
}
VTX 2125, 0, 0
{
COORD (620,1160)
}
BUS 2127, 0, 0
{
NET 2128
VTX 2124, 2125
VARIABLES
{
#NAMED="1"
}
}
NET BUS 2128, 0, 0
{
VARIABLES
{
#DECLARATION=""
#DOWNTO=""
#INITIAL_VALUE=""
#NAME="PORT1(3:0)"
#VHDL_TYPE=""
}
}
TEXT 2129, 0, 0
{
TEXT "$#NAME"
RECT (500,1131,630,1160)
ALIGN 8
MARGINS (1,1)
COLOR (0,0,255)
PARENT 2127
FONT (10,0,0,400,0,0,0,"Arial")
}
NET WIRE 2133, 0, 0
{
VARIABLES
{
#NAME="PORT3(2)"
}
}
TEXT 2134, 0, 0
{
TEXT "$#NAME"
RECT (500,1251,610,1280)
ALIGN 8
MARGINS (1,1)
COLOR (0,0,255)
PARENT 2082
FONT (10,0,0,400,0,0,0,"Arial")
}
VTX 2138, 0, 0
{
COORD (1560,1760)
}
VTX 2139, 0, 0
{
COORD (1420,1760)
}
WIRE 2141, 0, 0
{
NET 2142
VTX 2138, 2139
VARIABLES
{
#NAMED="1"
}
}
NET WIRE 2142, 0, 0
{
VARIABLES
{
#NAME="PORT3(1)"
}
}
TEXT 2143, 0, 0
{
TEXT "$#NAME"
RECT (1420,1731,1530,1760)
ALIGN 8
MARGINS (1,1)
COLOR (0,0,255)
PARENT 2141
FONT (10,0,0,400,0,0,0,"Arial")
}
VTX 2147, 0, 0
{
COORD (1880,1760)
}
NET WIRE 2151, 0, 0
{
VARIABLES
{
#NAME="PORT3(0)"
}
}
TEXT 2152, 0, 0
{
TEXT "$#NAME"
RECT (1900,1731,2010,1760)
ALIGN 8
MARGINS (1,1)
COLOR (0,0,255)
PARENT 2158
FONT (10,0,0,400,0,0,0,"Arial")
}
VTX 2156, 0, 0
{
COORD (2000,1760)
}
WIRE 2158, 0, 0
{
NET 2151
VTX 2147, 2156
VARIABLES
{
#NAMED="1"
}
}
VTX 2159, 0, 0
{
COORD (1880,1720)
}
VTX 2160, 0, 0
{
COORD (2000,1720)
}
WIRE 2162, 0, 0
{
NET 2163
VTX 2159, 2160
VARIABLES
{
#NAMED="1"
}
}
NET WIRE 2163, 0, 0
{
VARIABLES
{
#NAME="PORT3(3)"
}
}
TEXT 2164, 0, 0
{
TEXT "$#NAME"
RECT (1900,1691,2010,1720)
ALIGN 8
MARGINS (1,1)
COLOR (0,0,255)
PARENT 2162
FONT (10,0,0,400,0,0,0,"Arial")
}
VTX 2168, 0, 0
{
COORD (2840,1000)
}
VTX 2169, 0, 0
{
COORD (2660,1000)
}
WIRE 2171, 0, 0
{
NET 2172
VTX 2168, 2169
VARIABLES
{
#NAMED="1"
}
}
NET WIRE 2172, 0, 0
{
VARIABLES
{
#NAME="PORT3(4)"
}
}
TEXT 2173, 0, 0
{
TEXT "$#NAME"
RECT (2660,971,2770,1000)
ALIGN 8
MARGINS (1,1)
COLOR (0,0,255)
PARENT 2171
FONT (10,0,0,400,0,0,0,"Arial")
}
NET WIRE 2185, 0, 0
{
VARIABLES
{
#NAME="PORT3(5)"
}
}
TEXT 2186, 0, 0
{
TEXT "$#NAME"
RECT (2600,1391,2710,1420)
ALIGN 8
MARGINS (1,1)
COLOR (0,0,255)
PARENT 2196
FONT (10,0,0,400,0,0,0,"Arial")
}
VTX 2190, 0, 0
{
COORD (2840,1360)
}
VTX 2191, 0, 0
{
COORD (2620,1420)
}
VTX 2192, 0, 0
{
COORD (2800,1360)
}
WIRE 2193, 0, 0
{
NET 2185
VTX 2190, 2192
}
VTX 2194, 0, 0
{
COORD (2800,1420)
}
WIRE 2195, 0, 0
{
NET 2185
VTX 2192, 2194
}
WIRE 2196, 0, 0
{
NET 2185
VTX 2194, 2191
VARIABLES
{
#NAMED="1"
}
}
VTX 2197, 0, 0
{
COORD (2840,1100)
}
VTX 2198, 0, 0
{
COORD (2520,1100)
}
WIRE 2199, 0, 0
{
NET 1603
VTX 2197, 2198
}
VTX 2200, 0, 0
{
COORD (2520,1320)
}
WIRE 2201, 0, 0
{
NET 1603
VTX 2198, 2200
}
WIRE 2202, 0, 0
{
NET 1603
VTX 2200, 1586
}
NET BUS 2204, 0, 0
{
VARIABLES
{
#DECLARATION=""
#DOWNTO=""
#INITIAL_VALUE=""
#NAME="PORT0(7:0)"
#VHDL_TYPE=""
}
}
TEXT 2205, 0, 0
{
TEXT "$#NAME"
RECT (1277,409,1407,438)
ALIGN 8
MARGINS (1,1)
COLOR (0,0,255)
PARENT 1665
FONT (10,0,0,400,0,0,0,"Arial")
}
VTX 2283, 0, 0
{
COORD (760,1420)
}
BUS 2285, 0, 0
{
NET 2083
VTX 2045, 2283
BUSTAPS ( 2075, 2080, 2304 )
}
VTX 2302, 0, 0
{
COORD (1500,1100)
}
VTX 2303, 0, 0
{
COORD (1420,1380)
}
VTX 2304, 0, 0
{
COORD (760,1380)
}
VTX 2306, 0, 0
{
COORD (1420,1100)
}
WIRE 2307, 0, 0
{
NET 1598
VTX 2302, 2306
}
WIRE 2308, 0, 0
{
NET 1598
VTX 2306, 2303
}
WIRE 2309, 0, 0
{
NET 1598
VTX 2304, 2303
VARIABLES
{
#NAMED="1"
}
}
VTX 2326, 0, 0
{
COORD (2840,880)
}
VTX 2327, 0, 0
{
COORD (900,1260)
}
VTX 2328, 0, 0
{
COORD (2380,880)
}
WIRE 2329, 0, 0
{
NET 1243
VTX 2326, 2328
}
VTX 2330, 0, 0
{
COORD (2380,1260)
}
WIRE 2331, 0, 0
{
NET 1243
VTX 2328, 2330
}
WIRE 2332, 0, 0
{
NET 1243
VTX 2330, 2327
VARIABLES
{
#NAMED="1"
}
}
VTX 2339, 0, 0
{
COORD (2840,1220)
}
VTX 2340, 0, 0
{
COORD (2660,1220)
}
WIRE 2341, 0, 0
{
NET 1598
VTX 2339, 2340
}
VTX 2342, 0, 0
{
COORD (2660,1380)
}
WIRE 2343, 0, 0
{
NET 1598
VTX 2340, 2342
}
WIRE 2344, 0, 0
{
NET 1598
VTX 2342, 2303
}
TEXT 2345, 0, 0
{
TEXT "LATCH"
RECT (1660,300,1785,346)
MARGINS (1,1)
COLOR (128,0,128)
FONT (16,0,0,400,1,0,0,"Arial")
}
TEXT 2349, 0, 0
{
TEXT "RAM"
RECT (1680,880,1766,926)
MARGINS (1,1)
COLOR (128,0,128)
FONT (16,0,0,400,1,0,0,"Arial")
}
TEXT 2353, 0, 0
{
TEXT "PARALLEL - SERIAL REGISTER"
RECT (1500,1540,2074,1586)
MARGINS (1,1)
COLOR (128,0,128)
FONT (16,0,0,400,1,0,0,"Arial")
}
TEXT 2357, 0, 0
{
TEXT
"The Parallel - Serial Register is \n"+
"connected to Serial Port of 8051 \n"+
"Microcontroller. The Serial Port \n"+
"works in Mode 0."
RECT (1520,1940,1938,2066)
MARGINS (1,1)
COLOR (0,0,0)
FONT (12,0,0,400,1,0,0,"Arial")
MULTILINE
}
NET BUS 2590, 0, 0
BUS 2591, 0, 0
{
NET 2590
VTX 1939, 1935
BUSTAPS ( 1908, 2327 )
}
NET BUS 2601, 0, 0
{
VARIABLES
{
#DECLARATION=""
#DOWNTO=""
#INITIAL_VALUE=""
#NAME="ADD(7:0)"
#VHDL_TYPE=""
}
}
TEXT 2602, 0, 0
{
TEXT "$#NAME"
RECT (1932,409,2032,438)
ALIGN 8
MARGINS (1,1)
COLOR (0,0,255)
PARENT 1758
FONT (10,0,0,400,0,0,0,"Arial")
}
NET BUS 2606, 0, 0
{
VARIABLES
{
#DECLARATION=""
#DOWNTO=""
#INITIAL_VALUE=""
#NAME="ADD(4:0)"
#VHDL_TYPE=""
}
}
TEXT 2607, 0, 0
{
TEXT "$#NAME"
RECT (2432,729,2532,758)
ALIGN 8
MARGINS (1,1)
COLOR (0,0,255)
PARENT 1752
FONT (10,0,0,400,0,0,0,"Arial")
}
NET BUS 2611, 0, 0
{
VARIABLES
{
#DECLARATION=""
#DOWNTO=""
#INITIAL_VALUE=""
#NAME="ADD(3:0)"
#VHDL_TYPE=""
}
}
TEXT 2612, 0, 0
{
TEXT "$#NAME"
RECT (1632,729,1732,758)
ALIGN 8
MARGINS (1,1)
COLOR (0,0,255)
PARENT 1755
FONT (10,0,0,400,0,0,0,"Arial")
}
VTX 2616, 0, 0
{
COORD (1500,1020)
}
BUS 2617, 0, 0
{
NET 2611
VTX 2616, 1200
}
SIGNALASSIGN 2622, 0, 0
{
LABEL "SignalAssignments"
TEXT "PORT2<=\"ZZZZZZZZ\";"
RECT (920,1020,1224,1053)
COLOR (120,0,0)
FONT (12,0,0,400,0,0,0,"Arial")
MULTILINE
SYNTAXCOLORED
SHOWLABEL
SHOWTEXT
}
}
}
PAGE ""
{
PAGEHEADER
{
PAGESIZE (3307,2338)
MARGINS (200,200,200,200)
RECT (0,0,0,0)
VARIABLES
{
#BLOCKTABLE_PAGE="1"
#BLOCKTABLE_TEMPL="1"
#BLOCKTABLE_VISIBLE="0"
#MODIFIED="1004466010"
}
}
BODY
{
TEXT 2739, 0, 0
{
PAGEALIGN 10
OUTLINE 5,1, (0,0,0)
TEXT "Created:"
RECT (2247,2024,2364,2077)
ALIGN 4
MARGINS (1,10)
COLOR (0,0,0)
FONT (12,0,0,700,0,0,0,"Arial")
}
TEXT 2740, 0, 0
{
PAGEALIGN 10
TEXT "$CREATIONDATE"
RECT (2417,2018,3087,2078)
ALIGN 4
MARGINS (1,1)
COLOR (0,0,0)
FONT (12,0,0,700,0,0,0,"Arial")
UPDATE 0
}
TEXT 2741, 0, 0
{
PAGEALIGN 10
TEXT "Title:"
RECT (2248,2082,2319,2135)
ALIGN 4
MARGINS (1,10)
COLOR (0,0,0)
FONT (12,0,0,700,0,0,0,"Arial")
}
TEXT 2742, 0, 0
{
PAGEALIGN 10
OUTLINE 5,1, (0,0,0)
TEXT "$TITLE"
RECT (2417,2078,3087,2138)
ALIGN 4
MARGINS (1,1)
COLOR (0,0,0)
FONT (12,0,0,700,0,0,0,"Arial")
UPDATE 0
}
LINE 2743, 0, 0
{
PAGEALIGN 10
OUTLINE 0,1, (128,128,128)
POINTS ( (2237,2018), (3107,2018) )
FILL (1,(0,0,0),0)
}
LINE 2744, 0, 0
{
PAGEALIGN 10
OUTLINE 0,1, (128,128,128)
POINTS ( (2237,2078), (3107,2078) )
FILL (1,(0,0,0),0)
}
LINE 2745, 0, 0
{
PAGEALIGN 10
OUTLINE 0,1, (128,128,128)
POINTS ( (2407,2018), (2407,2138) )
}
LINE 2746, 0, 0
{
PAGEALIGN 10
OUTLINE 0,1, (128,128,128)
POINTS ( (3107,2138), (3107,1878), (2237,1878), (2237,2138), (3107,2138) )
FILL (1,(0,0,0),0)
}
TEXT 2747, 0, 0
{
PAGEALIGN 10
TEXT
"(C)ALDEC. Inc\n"+
"2260 Corporate Circle\n"+
"Henderson, NV 89074"
RECT (2247,1898,2542,1999)
MARGINS (1,1)
COLOR (0,0,0)
FONT (12,0,0,700,0,0,0,"Arial")
MULTILINE
}
LINE 2748, 0, 0
{
PAGEALIGN 10
OUTLINE 0,1, (128,128,128)
POINTS ( (2547,1878), (2547,2018) )
}
LINE 2749, 0, 0
{
PAGEALIGN 10
OUTLINE 0,4, (0,4,255)
POINTS ( (2723,1942), (2789,1942) )
FILL (0,(0,4,255),0)
}
LINE 2750, 0, 0
{
PAGEALIGN 10
OUTLINE 0,1, (0,4,255)
POINTS ( (2692,1938), (2692,1938) )
FILL (0,(0,4,255),0)
}
LINE 2751, 0, 0
{
PAGEALIGN 10
OUTLINE 0,3, (0,4,255)
POINTS ( (2741,1942), (2757,1902) )
FILL (0,(0,4,255),0)
}
TEXT 2752, -4, 0
{
PAGEALIGN 10
OUTLINE 5,0, (49,101,255)
TEXT "ALDEC"
RECT (2770,1884,3068,1986)
MARGINS (1,1)
COLOR (0,4,255)
FONT (36,0,0,700,0,1,0,"Arial")
}
LINE 2753, 0, 0
{
PAGEALIGN 10
OUTLINE 0,3, (0,4,255)
POINTS ( (2683,1902), (2658,1965) )
FILL (0,(0,4,255),0)
}
BEZIER 2754, 0, 0
{
PAGEALIGN 10
OUTLINE 0,3, (0,4,255)
FILL (0,(0,4,255),0)
ORIGINS ( (2690,1928), (2723,1942), (2690,1953), (2690,1928) )
CONTROLS (( (2714,1928), (2722,1927)),( (2720,1953), (2717,1953)),( (2690,1945), (2690,1940)) )
}
LINE 2755, 0, 0
{
PAGEALIGN 10
OUTLINE 0,4, (0,4,255)
POINTS ( (2602,1949), (2690,1949) )
FILL (0,(0,4,255),0)
}
LINE 2756, 0, 0
{
PAGEALIGN 10
OUTLINE 0,4, (0,4,255)
POINTS ( (2609,1932), (2690,1932) )
FILL (0,(0,4,255),0)
}
LINE 2757, 0, 0
{
PAGEALIGN 10
OUTLINE 0,1, (0,4,255)
POINTS ( (2795,1909), (2618,1909) )
FILL (0,(0,4,255),0)
}
LINE 2758, 0, 0
{
PAGEALIGN 10
OUTLINE 0,1, (0,4,255)
POINTS ( (2793,1916), (2615,1916) )
FILL (0,(0,4,255),0)
}
LINE 2759, 0, 0
{
PAGEALIGN 10
OUTLINE 0,1, (0,4,255)
POINTS ( (2807,1924), (2613,1924) )
FILL (0,(0,4,255),0)
}
LINE 2760, 0, 0
{
PAGEALIGN 10
OUTLINE 0,1, (0,4,255)
POINTS ( (2809,1932), (2617,1932) )
FILL (0,(0,4,255),0)
}
LINE 2761, 0, 0
{
PAGEALIGN 10
OUTLINE 0,1, (0,4,255)
POINTS ( (2722,1940), (2606,1940) )
FILL (0,(0,4,255),0)
}
LINE 2762, 0, 0
{
PAGEALIGN 10
OUTLINE 0,1, (0,4,255)
POINTS ( (2787,1949), (2602,1949) )
FILL (0,(0,4,255),0)
}
LINE 2763, 0, 0
{
PAGEALIGN 10
OUTLINE 0,1, (0,4,255)
POINTS ( (2780,1957), (2599,1957) )
FILL (0,(0,4,255),0)
}
TEXT 2764, 0, 0
{
PAGEALIGN 10
TEXT "The Design Verification Company"
RECT (2589,1974,3041,2008)
MARGINS (1,1)
COLOR (0,4,255)
FONT (12,0,0,700,1,1,0,"Arial")
}
LINE 2765, 0, 0
{
PAGEALIGN 10
OUTLINE 0,1, (0,4,255)
POINTS ( (2774,1965), (2596,1965) )
FILL (0,(0,4,255),0)
}
LINE 2766, 0, 0
{
PAGEALIGN 10
OUTLINE 0,1, (0,4,255)
POINTS ( (2797,1902), (2621,1902) )
FILL (0,(0,4,255),0)
}
}
}
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