fpga.bde

使用VHDL语言编写的8051IP核

   PARENT 42
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  INSTANCE  46, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="Output"
    #DOWNTO=""
    #INITIAL_VALUE=""
    #LIBRARY="#terminals"
    #REFERENCE="nCS"
    #SYMBOL="Output"
    #VHDL_TYPE=""
   }
   COORD (2840,880)
   VERTEXES ( (2,2326) )
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  {
   TEXT "$#REFERENCE"
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  INSTANCE  50, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="Output"
    #DOWNTO=""
    #INITIAL_VALUE=""
    #LIBRARY="#terminals"
    #REFERENCE="CTR"
    #SYMBOL="Output"
    #VHDL_TYPE=""
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   COORD (2840,1000)
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  TEXT  52, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (2895,984,2958,1019)
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   PARENT 50
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  INSTANCE  54, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="Output"
    #DOWNTO=""
    #INITIAL_VALUE=""
    #LIBRARY="#terminals"
    #REFERENCE="nRD"
    #SYMBOL="Output"
    #VHDL_TYPE=""
   }
   COORD (2840,1220)
   VERTEXES ( (2,2339) )
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  TEXT  56, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (2895,1204,2955,1239)
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   COLOR (0,0,192)
   PARENT 54
   FONT (12,0,0,400,0,0,0,"Arial")
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  INSTANCE  58, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="Output"
    #DOWNTO=""
    #INITIAL_VALUE=""
    #LIBRARY="#terminals"
    #REFERENCE="nWR"
    #SYMBOL="Output"
    #VHDL_TYPE=""
   }
   COORD (2840,1100)
   VERTEXES ( (2,2197) )
  }
  TEXT  60, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (2895,1084,2964,1119)
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   COLOR (0,0,192)
   PARENT 58
   FONT (12,0,0,400,0,0,0,"Arial")
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  INSTANCE  62, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="Latch"
    #LIBRARY="#default"
    #REFERENCE="U0"
    #SYMBOL="Latch"
   }
   COORD (1600,400)
   VERTEXES ( (4,1643), (7,1756), (10,1660) )
  }
  TEXT  63, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (1620,345,1659,380)
   ALIGN 8
   MARGINS (1,1)
   COLOR (0,0,192)
   PARENT 62
   FONT (12,0,0,400,0,0,0,"Arial")
  }
  TEXT  67, 0, 0
  {
   TEXT "$#COMPONENT"
   RECT (1620,540,1693,575)
   MARGINS (1,1)
   COLOR (0,128,0)
   PARENT 62
   FONT (12,0,0,400,0,0,0,"Arial")
  }
  INSTANCE  143, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="ram"
    #LIBRARY="#default"
    #REFERENCE="U1"
    #SYMBOL="ram"
   }
   COORD (1500,980)
   VERTEXES ( (7,1706), (10,1907), (13,2302), (16,1585), (23,2616) )
  }
  TEXT  144, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (1520,924,1559,959)
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   MARGINS (1,1)
   COLOR (0,0,192)
   PARENT 143
   FONT (12,0,0,400,0,0,0,"Arial")
  }
  TEXT  148, 0, 0
  {
   TEXT "$#COMPONENT"
   RECT (1520,1201,1573,1236)
   MARGINS (1,1)
   COLOR (0,128,0)
   PARENT 143
   FONT (12,0,0,400,0,0,0,"Arial")
  }
  INSTANCE  158, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="pr_sr_register"
    #LIBRARY="#default"
    #REFERENCE="U2"
    #SYMBOL="pr_sr_register"
   }
   COORD (1560,1640)
   VERTEXES ( (4,1887), (7,1797), (10,1877), (13,2159), (16,2138), (19,2147), (22,1804) )
  }
  TEXT  159, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (1580,1584,1619,1619)
   ALIGN 8
   MARGINS (1,1)
   COLOR (0,0,192)
   PARENT 158
   FONT (12,0,0,400,0,0,0,"Arial")
  }
  TEXT  163, 0, 0
  {
   TEXT "$#COMPONENT"
   RECT (1580,1861,1763,1896)
   MARGINS (1,1)
   COLOR (0,128,0)
   PARENT 158
   FONT (12,0,0,400,0,0,0,"Arial")
  }
  INSTANCE  767, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="BusInput"
    #DECLARATION=""
    #DOWNTO=""
    #INITIAL_VALUE=""
    #LIBRARY="#terminals"
    #REFERENCE="DATAS(7:0)"
    #SYMBOL="BusInput"
    #VHDL_TYPE=""
   }
   COORD (460,1520)
   VERTEXES ( (2,1888) )
  }
  TEXT  769, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (246,1504,405,1539)
   ALIGN 2
   MARGINS (1,1)
   COLOR (0,0,192)
   PARENT 767
   FONT (12,0,0,400,0,0,0,"Arial")
  }
  INSTANCE  771, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="Input"
    #DOWNTO=""
    #INITIAL_VALUE=""
    #LIBRARY="#terminals"
    #REFERENCE="nWRS"
    #SYMBOL="Input"
    #VHDL_TYPE=""
   }
   COORD (460,1640)
   VERTEXES ( (2,1803) )
  }
  TEXT  773, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (317,1624,405,1659)
   ALIGN 2
   MARGINS (1,1)
   COLOR (0,0,192)
   PARENT 771
   FONT (12,0,0,400,0,0,0,"Arial")
  }
  INSTANCE  775, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="Output"
    #DOWNTO=""
    #INITIAL_VALUE=""
    #LIBRARY="#terminals"
    #REFERENCE="BUSY"
    #SYMBOL="Output"
    #VHDL_TYPE=""
   }
   COORD (2840,1480)
   VERTEXES ( (2,1796) )
  }
  TEXT  777, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (2895,1464,2975,1499)
   MARGINS (1,1)
   COLOR (0,0,192)
   PARENT 775
   FONT (12,0,0,400,0,0,0,"Arial")
  }
  NET WIRE  904, 0, 0
  VTX  1200, 0, 0
  {
   COORD (1240,1020)
  }
  NET WIRE  1213, 0, 0
  {
   VARIABLES
   {
    #NAME="PORT2(7)"
   }
  }
  TEXT  1214, 0, 0
  {
   TEXT "$#NAME"
   RECT (1065,1111,1175,1140)
   ALIGN 8
   MARGINS (1,1)
   COLOR (0,0,255)
   PARENT 1920
   FONT (10,0,0,400,0,0,0,"Arial")
  }
  NET WIRE  1243, 0, 0
  {
   VARIABLES
   {
    #NAME="PORT2(6)"
   }
  }
  TEXT  1244, 0, 0
  {
   TEXT "$#NAME"
   RECT (1660,1231,1770,1260)
   ALIGN 8
   MARGINS (1,1)
   COLOR (0,0,255)
   PARENT 2332
   FONT (10,0,0,400,0,0,0,"Arial")
  }
  NET BUS  1260, 0, 0
  NET WIRE  1366, 0, 0
  NET WIRE  1374, 0, 0
  NET WIRE  1378, 0, 0
  VTX  1585, 0, 0
  {
   COORD (1500,1140)
  }
  VTX  1586, 0, 0
  {
   COORD (1480,1320)
  }
  VTX  1589, 0, 0
  {
   COORD (1480,1140)
  }
  WIRE  1590, 0, 0
  {
   NET 1603
   VTX 1585, 1589
  }
  WIRE  1591, 0, 0
  {
   NET 1603
   VTX 1589, 1586
  }
  NET WIRE  1598, 0, 0
  {
   VARIABLES
   {
    #NAME="PORT3(7)"
   }
  }
  TEXT  1599, 0, 0
  {
   TEXT "$#NAME"
   RECT (1059,1351,1169,1380)
   ALIGN 8
   MARGINS (1,1)
   COLOR (0,0,255)
   PARENT 2309
   FONT (10,0,0,400,0,0,0,"Arial")
  }
  NET WIRE  1603, 0, 0
  {
   VARIABLES
   {
    #NAME="PORT3(6)"
   }
  }
  TEXT  1604, 0, 0
  {
   TEXT "$#NAME"
   RECT (1058,1291,1168,1320)
   ALIGN 8
   MARGINS (1,1)
   COLOR (0,0,255)
   PARENT 2078
   FONT (10,0,0,400,0,0,0,"Arial")
  }
  VTX  1642, 0, 0
  {
   COORD (440,560)
  }
  VTX  1643, 0, 0
  {
   COORD (1600,480)
  }
  VTX  1644, 0, 0
  {
   COORD (780,560)
  }
  WIRE  1645, 0, 0
  {
   NET 904
   VTX 1642, 1644
  }
  VTX  1646, 0, 0
  {
   COORD (780,480)
  }
  WIRE  1647, 0, 0
  {
   NET 904
   VTX 1644, 1646
  }
  WIRE  1648, 0, 0
  {
   NET 904
   VTX 1646, 1643
  }
  VTX  1659, 0, 0
  {
   COORD (1080,640)
  }
  VTX  1660, 0, 0
  {
   COORD (1600,440)
  }
  VTX  1664, 0, 0
  {
   COORD (1080,440)
  }
  BUS  1665, 0, 0
  {
   NET 2204
   VTX 1660, 1664
   VARIABLES
   {
    #NAMED="1"
   }
  }
  BUS  1666, 0, 0
  {
   NET 2204
   VTX 1664, 1659
  }
  VTX  1690, 0, 0
  {
   COORD (460,680)
  }
  VTX  1691, 0, 0
  {
   COORD (660,680)
  }
  BUS  1692, 0, 0
  {
   NET 2204
   VTX 1690, 1691
  }
  VTX  1693, 0, 0
  {
   COORD (660,640)
  }
  BUS  1694, 0, 0
  {
   NET 2204
   VTX 1659, 1693
  }
  BUS  1695, 0, 0
  {
   NET 2204
   VTX 1693, 1691
  }
  VTX  1706, 0, 0
  {
   COORD (1940,1020)
  }
  VTX  1707, 0, 0
  {
   COORD (2220,640)
  }
  VTX  1709, 0, 0
  {
   COORD (2220,1020)
  }
  BUS  1710, 0, 0
  {
   NET 2204
   VTX 1706, 1709
  }
  BUS  1711, 0, 0
  {
   NET 2204
   VTX 1709, 1707
  }
  BUS  1712, 0, 0
  {
   NET 2204
   VTX 1659, 1707
  }
  VTX  1738, 0, 0
  {
   COORD (2120,760)
  }
  VTX  1739, 0, 0
  {
   COORD (2840,760)
  }
  BUS  1752, 0, 0
  {
   NET 2606
   VTX 1739, 1738
   VARIABLES
   {
    #NAMED="1"
   }
  }
  VTX  1753, 0, 0
  {
   COORD (1240,760)
  }
  BUS  1754, 0, 0
  {
   NET 2611
   VTX 1200, 1753
  }
  BUS  1755, 0, 0
  {
   NET 2611
   VTX 1753, 1738
   VARIABLES
   {
    #NAMED="1"
   }
  }
  VTX  1756, 0, 0
  {
   COORD (1840,440)
  }
  VTX  1757, 0, 0
  {
   COORD (2120,440)
  }
  BUS  1758, 0, 0
  {
   NET 2601
   VTX 1756, 1757
   VARIABLES
   {
    #NAMED="1"
   }
  }
  BUS  1759, 0, 0
  {
   NET 2601
   VTX 1757, 1738
  }
  VTX  1796, 0, 0
  {
   COORD (2840,1480)
  }
  VTX  1797, 0, 0
  {
   COORD (1880,1680)
  }
  VTX  1798, 0, 0
  {
   COORD (2580,1480)
  }
  WIRE  1799, 0, 0
  {
   NET 1366
   VTX 1796, 1798
  }
  VTX  1800, 0, 0
  {
   COORD (2580,1680)
  }
  WIRE  1801, 0, 0
  {
   NET 1366
   VTX 1798, 1800
  }
  WIRE  1802, 0, 0
  {
   NET 1366
   VTX 1800, 1797
  }
  VTX  1803, 0, 0
  {
   COORD (460,1640)
  }
  VTX  1804, 0, 0
  {
   COORD (1560,1800)
  }
  VTX  1805, 0, 0
  {
   COORD (480,1640)
  }
  WIRE  1806, 0, 0
  {
   NET 1374
   VTX 1803, 1805
  }
  VTX  1807, 0, 0
  {
   COORD (480,1800)
  }
  WIRE  1808, 0, 0
  {
   NET 1374
   VTX 1805, 1807
  }
  WIRE  1809, 0, 0
  {
   NET 1374
   VTX 1807, 1804
  }
  VTX  1876, 0, 0
  {
   COORD (460,1400)
  }
  VTX  1877, 0, 0
  {
   COORD (1560,1720)
  }
  VTX  1878, 0, 0
  {
   COORD (540,1400)
  }
  WIRE  1879, 0, 0
  {
   NET 1378
   VTX 1876, 1878
  }
  VTX  1880, 0, 0
  {
   COORD (540,1460)
  }
  WIRE  1881, 0, 0
  {
   NET 1378
   VTX 1878, 1880
  }
  VTX  1882, 0, 0
  {
   COORD (1200,1460)
  }
  WIRE  1883, 0, 0
  {
   NET 1378
   VTX 1880, 1882
  }
  VTX  1884, 0, 0
  {
   COORD (1200,1720)
  }
  WIRE  1885, 0, 0
  {
   NET 1378
   VTX 1882, 1884
  }
  WIRE  1886, 0, 0
  {
   NET 1378
   VTX 1884, 1877
  }
  VTX  1887, 0, 0
  {
   COORD (1560,1680)
  }
  VTX  1888, 0, 0
  {
   COORD (460,1520)
  }
  VTX  1889, 0, 0
  {
   COORD (620,1680)
  }
  BUS  1890, 0, 0
  {
   NET 1260
   VTX 1887, 1889
  }
  VTX  1891, 0, 0
  {
   COORD (620,1520)
  }
  BUS  1892, 0, 0
  {
   NET 1260
   VTX 1889, 1891
  }
  BUS  1893, 0, 0
  {
   NET 1260
   VTX 1891, 1888
  }
  VTX  1907, 0, 0
  {
   COORD (1500,1060)
  }
  VTX  1908, 0, 0
  {
   COORD (900,1140)
  }
  VTX  1916, 0, 0
  {
   COORD (1260,1060)
  }
  WIRE  1917, 0, 0
  {
   NET 1213
   VTX 1907, 1916
  }
  VTX  1918, 0, 0
  {
   COORD (1260,1140)
  }
  WIRE  1919, 0, 0
  {
   NET 1213
   VTX 1916, 1918
  }
  WIRE  1920, 0, 0
  {
   NET 1213
   VTX 1918, 1908
   VARIABLES
   {
    #NAMED="1"
   }
  }
  VTX  1935, 0, 0
  {
   COORD (900,1300)
  }
  VTX  1936, 0, 0
  {
   COORD (460,920)
  }
  VTX  1939, 0, 0
  {
   COORD (900,920)
  }
  BUS  1940, 0, 0
  {
   NET 2590
   VTX 1936, 1939
  }
  VTX  2043, 0, 0
  {
   COORD (460,1040)
  }
  VTX  2045, 0, 0
  {
   COORD (760,1040)
  }
  BUS  2046, 0, 0
  {
   NET 2083
   VTX 2043, 2045
  }
  VTX  2075, 0, 0
  {
   COORD (760,1320)
  }
  WIRE  2078, 0, 0
  {
   NET 1603
   VTX 1586, 2075
   VARIABLES
   {
    #NAMED="1"
   }
  }
  VTX  2079, 0, 0
  {
   COORD (460,1280)
  }
  VTX  2080, 0, 0
  {
   COORD (760,1280)
  }
  WIRE  2082, 0, 0
  {
   NET 2133
   VTX 2079, 2080
   VARIABLES
   {
    #NAMED="1"
   }
  }
  NET BUS  2083, 0, 0
  NET BUS  2116, 0, 0
  {
   VARIABLES
   {
    #DECLARATION=""
    #DOWNTO=""
    #INITIAL_VALUE=""
    #NAME="PORT1(7:0)"
    #VHDL_TYPE=""
   }
  }
  TEXT  2117, 0, 0
  {
   TEXT "$#NAME"
   RECT (500,771,630,800)
   ALIGN 8
   MARGINS (1,1)
   COLOR (0,0,255)
   PARENT 2123
   FONT (10,0,0,400,0,0,0,"Arial")
  }