a8051_exp.bde

使用VHDL语言编写的8051IP核

  }
  NET WIRE  2333, 0, 0
  {
   VARIABLES
   {
    #NAME="ACKA"
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  }
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   TEXT "$#NAME"
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  TEXT  2338, 0, 0
  {
   TEXT "$#NAME"
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  {
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  {
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  WIRE  2344, 0, 0
  {
   NET 2333
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   {
    #NAMED="1"
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  {
   COORD (1460,1300)
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  {
   COORD (2680,1720)
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  {
   COORD (1400,1300)
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  BUS  2411, 0, 0
  {
   NET 2539
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  VTX  2412, 0, 0
  {
   COORD (1400,1720)
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  BUS  2413, 0, 0
  {
   NET 2539
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  BUS  2414, 0, 0
  {
   NET 2539
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   VARIABLES
   {
    #NAMED="1"
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  VTX  2415, 0, 0
  {
   COORD (1460,1260)
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  {
   COORD (2680,1800)
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  {
   COORD (1320,1260)
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  WIRE  2418, 0, 0
  {
   NET 2298
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  VTX  2419, 0, 0
  {
   COORD (1320,1800)
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  {
   NET 2298
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  WIRE  2421, 0, 0
  {
   NET 2298
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   {
    #NAMED="1"
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  {
   COORD (1460,1100)
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  {
   COORD (460,1100)
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  {
   COORD (640,1500)
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    #NAMED="1"
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  {
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  {
   NET 686
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  {
   NET 686
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  {
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  {
   NET 686
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  {
   COORD (440,580)
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  WIRE  2497, 0, 0
  {
   NET 686
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  VTX  2501, 0, 0
  {
   COORD (1460,1140)
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  VTX  2502, 0, 0
  {
   COORD (900,1680)
  }
  VTX  2503, 0, 0
  {
   COORD (1120,1140)
  }
  BUS  2504, 0, 0
  {
   NET 823
   VTX 2501, 2503
   VARIABLES
   {
    #NAMED="1"
   }
  }
  VTX  2505, 0, 0
  {
   COORD (1120,1680)
  }
  BUS  2506, 0, 0
  {
   NET 823
   VTX 2503, 2505
  }
  BUS  2507, 0, 0
  {
   NET 823
   VTX 2505, 2502
  }
  TEXT  2508, 0, 0
  {
   OUTLINE 5,1, (0,128,0)
   TEXT "FPGA DEVICE"
   RECT (1620,780,1875,826)
   MARGINS (1,1)
   COLOR (128,0,128)
   FONT (16,0,0,400,1,0,0,"Arial")
   FILL (1,(116,32,116),0)
  }
  TEXT  2512, 0, 0
  {
   TEXT "DISPLAY MODULE"
   RECT (2480,340,2813,386)
   MARGINS (1,1)
   COLOR (128,0,128)
   FONT (16,0,0,400,1,0,0,"Arial")
  }
  TEXT  2516, 0, 0
  {
   TEXT 
"KEYBOARD CONTROL\n"+
"            LOGIC"
   RECT (580,1300,987,1390)
   MARGINS (1,1)
   COLOR (128,0,128)
   FONT (16,0,0,400,1,0,0,"Arial")
   MULTILINE
  }
  TEXT  2520, 0, 0
  {
   TEXT "MICROCONTROLLER 8051"
   RECT (660,300,1141,346)
   MARGINS (1,1)
   COLOR (128,0,128)
   FONT (16,0,0,400,1,0,0,"Arial")
   MULTILINE
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  {
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  {
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  {
   COORD (2320,1280)
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  WIRE  2527, 0, 0
  {
   NET 2303
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   VARIABLES
   {
    #NAMED="1"
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  }
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  {
   COORD (2320,1640)
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  {
   NET 2303
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  }
  WIRE  2530, 0, 0
  {
   NET 2303
   VTX 2528, 2525
  }
  TEXT  2535, 0, 0
  {
   TEXT 
"PINS OF PARALLEL - SERIAL REGISTER \n"+
"CONNECTED TO SERIAL PORT OF 8051"
   RECT (2460,1520,3010,1584)
   MARGINS (1,1)
   COLOR (128,0,128)
   FONT (12,0,0,400,1,0,0,"Arial")
   MULTILINE
  }
  NET BUS  2539, 0, 0
  {
   VARIABLES
   {
    #DECLARATION=""
    #DOWNTO=""
    #INITIAL_VALUE=""
    #NAME="DATAS(7:0)"
    #VHDL_TYPE=""
   }
  }
  VTX  2542, 0, 0
  {
   COORD (2080,960)
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  {
   COORD (2160,540)
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  VTX  2550, 0, 0
  {
   COORD (2160,960)
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  BUS  2552, 0, 0
  {
   NET 2556
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  }
  BUS  2553, 0, 0
  {
   NET 2556
   VTX 2542, 2550
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  VTX  2554, 0, 0
  {
   COORD (2480,540)
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  BUS  2555, 0, 0
  {
   NET 2556
   VTX 2549, 2554
   VARIABLES
   {
    #NAMED="1"
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  }
  NET BUS  2556, 0, 0
  {
   VARIABLES
   {
    #DECLARATION=""
    #DOWNTO=""
    #NAME="ADDRESS(4:0)"
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  }
  TEXT  2557, 0, 0
  {
   TEXT "$#NAME"
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  VTX  2581, 0, 0
  {
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  TEXT  2584, 0, 0
  {
   TEXT "$#NAME"
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  {
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  BUS  2589, 0, 0
  {
   NET 118
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  BUS  2591, 0, 0
  {
   NET 118
   VTX 2581, 2588
   VARIABLES
   {
    #NAMED="1"
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  }
  INSTANCE  2596, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="AL8051"
    #LIBRARY="#default"
    #REFERENCE="U0"
    #SYMBOL="al8051"
   }
   COORD (640,460)
   VERTEXES ( (4,2646), (7,2648), (10,2650), (16,2651), (19,2652), (22,2654), (25,2656), (28,2658) )
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  TEXT  2597, 0, 0
  {
   TEXT "$#REFERENCE"
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  TEXT  2601, 0, 0
  {
   TEXT "$#COMPONENT"
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   PARENT 2596
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  VTX  2645, 0, 0
  {
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  {
   COORD (640,500)
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  {
   COORD (1460,1060)
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  {
   COORD (640,540)
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  {
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   COORD (960,540)
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   COORD (1460,940)
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  {
   COORD (960,580)
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  {
   COORD (1460,980)
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   COORD (960,620)
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  {
   COORD (1460,1020)
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  {
   COORD (960,660)
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  {
   NET 22
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  {
   NET 150
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   {
    #NAMED="1"
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   COORD (520,620)
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   NET 150
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   NET 35
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  {
   NET 35
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   NET 686
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   NET 118
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   NET 123
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    #NAMED="1"
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  {
   COORD (1240,580)
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   NET 123
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   NET 123
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   COORD (1160,980)
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    #NAMED="1"
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   NET 128
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   NET 128
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   COORD (1080,1020)
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   NET 133
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   {
    #NAMED="1"
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  {
   COORD (1080,660)
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   NET 133
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  BUS  2684, 0, 0
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   NET 133
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  VHDLDESIGNUNITHDR  2713, 0, 0
  {
   LABEL "Design Unit Header"
   TEXT 
"library IEEE;\n"+
"use IEEE.std_logic_1164.all;\n"+
"use WORK.types.all;"
   RECT (1320,240,1729,379)
   MARGINS (20,20)
   COLOR (120,0,0)
   FONT (12,0,0,400,0,0,0,"Arial")
   MULTILINE
   SYNTAXCOLORED
   SHOWLABEL
   SHOWTEXT
  }
  INSTANCE  2714, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="FPGA"
    #LIBRARY="#default"
    #REFERENCE="U1"
    #SYMBOL="FPGA"
   }
   COORD (1460,860)
   VERTEXES ( (3,1501), (8,2653), (13,2655), (18,2657), (23,2647), (28,2473), (31,2501), (34,2542), (37,1856), (50,2259), (55,2238), (60,2231), (65,2217), (70,2342), (75,2524), (77,2408), (83,2415) )
  }
  TEXT  2715, 0, 0
  {
   TEXT "$#COMPONENT"
   RECT (1460,1360,1541,1395)
   MARGINS (1,1)
   PARENT 2714
  }
  TEXT  2719, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (1460,824,1499,859)
   ALIGN 8
   MARGINS (1,1)
   PARENT 2714
  }
 }
 
}

PAGE ""
{
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 BODY
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  TEXT  2779, 0, 0
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   PAGEALIGN 10
   OUTLINE 5,1, (0,0,0)
   TEXT "Created:"
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   TEXT "$CREATIONDATE"
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   TEXT "Title:"
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   COLOR (0,0,0)
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   TEXT "$TITLE"
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   PAGEALIGN 10
   TEXT 
"(C)ALDEC. Inc\n"+
"2260 Corporate Circle\n"+
"Henderson, NV 89074"
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   TEXT "ALDEC"
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  TEXT  2804, 0, 0
  {
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   TEXT "The Design Verification Company"
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}