readme.txt

使用VHDL语言编写的8051IP核

IPCore8051 SAMPLE DESIGN.

This is the sample design with the behavioral 8051 microcontroller model.

The model is fully compatible with the family of 8051 microcontrollers.

Its internal memory contents is loaded from an external file (in Intel(tm) HEX format).

Aldec supports also synthesisable model of the 8051 device and other useful models.
You can contact Aldec ([e-mail]) for further details.

INTRODUCTION

The design has a hierarchical structure. The A8051_exp.bde file is the top level file of the design.   
The file contains the following modules:
- AL8051 microcontroller - the behavioral model of the 8051 microcontroller.
- Keyboard control logic module. 
This module imitates a simple external keyboard. 
It generates an external interrupt signal for the AL8051 module if any of the virtual keys is pressed.
The interrupt routine executed from the internal microcontroller memory reads the code of the key.
- Display module - This module is quite similar to a memory: there are 32 address locations corresponded to 32 characters on a virtual screen. 
ASCII character codes are written to the internal display memory and then they are displayed on the screen.
New data inside the display memory are accepted by a special command which must be written to the control register of the display.
- FPGA device - This module contains another part of the design, which can be synthesized. 
The FPGA device contains the following modules:
	- Latch - necessary to connect external devices to the 8051 device.
	- RAM - 16 bytes RAM memory.
	- Parallel-Serial Register - connected to the serial port of the 8051 device.
Parallel data on the DATAS input can by written to this register on the rising edge of the nWRS signal. 
The register generates an external interrupt signal if any single byte was written into it. 
Data are read by the serial port of the 8051 module.

SYNTHESIS AND PLACE & ROUTE.

The synthesis was done under the Exemplar Leonardo(tm) software targetted to the Actel A32300DXV device.
The software generates a VHDL file for the post-synthesis simulation. 
Before the simulation, you need to modify the file and add the appropriate VHDL library declaration. 
Active-HDL supports necessary libraries to all Actel devices. 
The modified file is attached to the design. 
The place & route was done under the Actel Designer(tm) software. 
It generates VHDL and SDF files for the timing simulation. 
Both files are also attached to the design. 
In addition, there is the attached EDIF file generated by the Exemplar software. 
The behavioral, post-synthesis and timing simulation can be performed using the same testbench file. 


HOW DOES IT WORK?

The design behavior depends on the program which is executed in the 8051 device. 
The program source code used in the sample design is saved in the PROGRAM.ASM file which is located in the design folder. 
When the simulation starts, the program displays the following message on the screen:
	 *** HELLO ***
	 IP Core 8051
After a while, the upper row of the display will change to:
	PRESS ANY KEY
	IP Core 8051
If you set a logical value 1 to any of the keyboard module input signals, the program displays the key number. 
For example, if you set '1' to the KEY_5 signal (virtual key '5' was pressed) the following message appears on the screen:
	PRESS ANY KEY
	KEY NUMBER 5
If you stimulate input signals of the keyboard control module, the module generates an external interrupt signal. 
You can observe how the interrupt is handled.

The parallel-serial register waits for data all the time.
If data are written, the register generates an external interrupt signal INT1. 
The service routine of this interrupt activates the 8051 microcontroller serial port. The port works in the "mode 0". 
The port generates another internal interrupt signal when data were received. 
The interrupt service routine reads the data from the internal SBUF register and writes data to the external RAM memory. 
You can observe how interrupts are handled and how the serial port works.

HOW TO RUN THE TESTBENCH.

A. General information.

The testbench folder contains the following files:
- A8051_exp_TB.vhd - Stimulators for the UUT (Unit Under Test).
- A8051_exp_TB_post_synth_cfg.vhd - The configuration file for the post-synthesis simulation.
- A8051_exp_TB_timing_cfg.vhd - The configuration file for the timing simulation.
- A8051_exp_TB_behavior.do - This macro performs the behavioral simulation.
- A8051_exp_TB_post_synth.do - This macro performs the post-synthesis simulation.
- A8051_exp_TB_timing.do - This macro performs the timing simulation. 

Macros contain the PAUSE instruction. Simulation is stopped for a while several times to observe the testbench execution process.
The behavioral simulation can show more details about behavior of the design than post-synthesis or timing simulation.
The FPGA DEVICE component was synthesized as the one part and its internal components cannot be extracted. 
The component must be considered as the one integrated part during the post-synthesis and timing simulation. 

B. Behavioral simulation.

The behavioral simulation is stopped seven times to demonstrate behavior of the design:
1. First, the message appears: *** HELLO ***, IP Core 8051. (Waveform: DISLAY.AWF, signal: SCREEN).
2. The next message is: PRESS ANY KEY, IP Core 8051. (Waveform: DISPLAY.AWF, signal SCREEN).   
The data byte was written to the parallel-serial register. (Waveform PR_SR_REGISTER.AWF, Signal: nWRS, Time 258.2 us).
3. The byte was received. (Waveform: PR_SR_REGISTER.AWF, signal TXD, Time: 259.62 - 261.54 us).
and the "key 0" has been pressed. (KEYBOARD.AWF, Signal KEY_0, Time 269.1 us).
4. The message appears: PRESS ANY KEY, KEY NUMBER 0. (Waveform: DISPLAY.AWF, Signal SCREEN, Time 363 us). 

The next three stops are similar to stops 2, 3 and 4.

C. Post-synthesis and timing simulation. 

During the post-synthesis and timing simulation the waveform PR_SR_REGISTER.AWF is not open because the parallel-serial register is included in 
the FPGA DEVICE component, which was synthesized as the one part. 
If you want to observe TXD and TXC signals of the register, note these signals are connected to P3.0 and P3.1 bits of the port 3 of the microcontroller.