avrread26l.lst

接触式IC卡的读写函数

__text_start:
__start:
    0017 EDCF      LDI	R28,0xDF
    0018 E0D0      LDI	R29,0
    0019 BFCD      OUT	0x3D,R28
    001A BFDE      OUT	0x3E,R29
    001B 51C0      SUBI	R28,0x10
    001C 40D0      SBCI	R29,0
    001D EA0A      LDI	R16,0xAA
    001E 8308      STD	Y+0,R16
    001F 2400      CLR	R0
    0020 E7E5      LDI	R30,0x75
    0021 E0F0      LDI	R31,0
    0022 E010      LDI	R17,0
    0023 37E5      CPI	R30,0x75
    0024 07F1      CPC	R31,R17
    0025 F011      BEQ	0x0028
    0026 9201      ST	R0,Z+
    0027 CFFB      RJMP	0x0023
    0028 8300      STD	Z+0,R16
    0029 E1E8      LDI	R30,0x18
    002A E0F0      LDI	R31,0
    002B E6A0      LDI	R26,0x60
    002C E0B0      LDI	R27,0
    002D E010      LDI	R17,0
    002E 32ED      CPI	R30,0x2D
    002F 07F1      CPC	R31,R17
    0030 F021      BEQ	0x0035
    0031 95C8      LPM
    0032 9631      ADIW	R30,1
    0033 920D      ST	R0,X+
    0034 CFF9      RJMP	0x002E
    0035 D210      RCALL	_main
_exit:
    0036 CFFF      RJMP	_exit
FILE: G:\AVR\AVR实例程序\实例源文件\read26\26L.C
(0001) #include "iot26v.h"
(0002) #include "macros.h"
(0003) 
(0004) #define uchar unsigned char
(0005) #define uint unsigned int
(0006) 
(0007) #define anjianweikai DDRA|=(1<<7);PORTA&=~(1<<7);
(0008) #define anjianweiguan DDRA&=~(1<<7);
(0009) 
(0010) #define fengmingkai PORTB|=(1<<6);PORTB|=(1<<7);
(0011) #define fengmingguan PORTB&=~(1<<6);PORTB&=~(1<<7);
(0012) 
(0013) #define rst0 PORTB&=~(1<<5) 
(0014) #define rst1 PORTB|=(1<<5) 
(0015) #define sda0 DDRB|=(1<<0);PORTB&=~(1<<0); 
(0016) #define sda1 DDRB|=(1<<0);PORTB|=(1<<0); 
(0017) #define scl0 DDRB|=(1<<2);PORTB&=~(1<<2); 
(0018) #define scl1 DDRB|=(1<<2);PORTB|=(1<<2); 
(0019) #define sdawei DDRB&=~(1<<0);PORTB|=(1<<0);
(0020) 
(0021) 
(0022) unsigned char com1=6,com2=5,cnt1=0;
(0023) unsigned int temp=0,qiangdu=368;
(0024) 
(0025) unsigned char disp[]={0xc0,0xf9,0xa4,0xb0,0x99,0x92,0x82,0xf8,0x80,0x90};
(0026) signed char kashu[2]={3,0};
(0027) unsigned char kawei=1,jianshu=0;
(0028) 
(0029) uchar x24c02_read(uchar address);  //从24c02的地址address中读取一个字节数据
(0030) void x24c02_write(uchar address,uchar info);//向24c02的address地址中写入一字节数据info
(0031) void x24c02_init(void);   //24c02初始化子程序
(0032) void delay1(uchar x);
(0033) void x24c01_init(void);
(0034) void start(void);
(0035) void stop(void);
(0036) void writex(uchar j);
(0037) unsigned char readx(void);
(0038) void clock(void);
(0039) /*延时函数*/
(0040) void delayus(int a)             //微秒级
(0041) {
(0042)   do
(0043)   a--; 
_delayus:
  a                    --> R16
    0037 5001      SUBI	R16,1
    0038 4010      SBCI	R17,0
(0044)  while(a>1);
    0039 E081      LDI	R24,1
    003A E090      LDI	R25,0
    003B 1780      CP	R24,R16
    003C 0791      CPC	R25,R17
    003D F3CC      BLT	0x0037
    003E 9508      RET
_delayms:
  a                    --> R20
    003F D228      RCALL	push_gset1
    0040 2F40      MOV	R20,R16
    0041 2F51      MOV	R21,R17
(0045)  //WDR();
(0046) }
(0047) 
(0048) void delayms(unsigned int a)        //毫秒级
(0049) {
    0042 C005      RJMP	0x0048
(0050)  while(a!=0)
(0051)  {
(0052)   delayus(250);
    0043 EF0A      LDI	R16,0xFA
    0044 E010      LDI	R17,0
    0045 DFF1      RCALL	_delayus
(0053)   a--;
    0046 5041      SUBI	R20,1
    0047 4050      SBCI	R21,0
    0048 3040      CPI	R20,0
    0049 0745      CPC	R20,R21
    004A F7C1      BNE	0x0043
    004B D21F      RCALL	pop_gset1
    004C 9508      RET
_fengming:
  a                    --> R20
    004D D21A      RCALL	push_gset1
    004E 2F40      MOV	R20,R16
(0054)  }
(0055) }
(0056) 
(0057) void fengming(unsigned char a)             ////蜂鸣器
(0058) {
(0059)     fengmingkai;
    004F 9AC6      SBI	0x18,6
    0050 9AC7      SBI	0x18,7
    0051 C004      RJMP	0x0056
(0060) 	while(a>1)
(0061) 	{
(0062) 	a--;
    0052 954A      DEC	R20
(0063) 	delayms(1);
    0053 E001      LDI	R16,1
    0054 E010      LDI	R17,0
    0055 DFE9      RCALL	_delayms
    0056 E081      LDI	R24,1
    0057 1784      CP	R24,R20
    0058 F3C8      BCS	0x0052
(0064) 	}
(0065) 	fengmingguan;
    0059 98C6      CBI	0x18,6
    005A 98C7      CBI	0x18,7
    005B D20F      RCALL	pop_gset1
    005C 9508      RET
(0066) }	
(0067) 
(0068) void x24c02_init(void)
(0069) {
(0070)    scl1; delayus(1); sda1; delayus(1);
_x24c02_init:
    005D 9ABA      SBI	0x17,2
    005E 9AC2      SBI	0x18,2
    005F E001      LDI	R16,1
    0060 E010      LDI	R17,0
    0061 DFD5      RCALL	_delayus
    0062 9AB8      SBI	0x17,0
    0063 9AC0      SBI	0x18,0
    0064 E001      LDI	R16,1
    0065 E010      LDI	R17,0
    0066 DFD0      RCALL	_delayus
    0067 9508      RET
(0071) }
(0072) void start(void)
(0073) {
(0074)    sda1; delayus(1); scl1;delayus(1); sda0; delayus(1); scl0; delayus(1);
_start:
    0068 9AB8      SBI	0x17,0
    0069 9AC0      SBI	0x18,0
    006A E001      LDI	R16,1
    006B E010      LDI	R17,0
    006C DFCA      RCALL	_delayus
    006D 9ABA      SBI	0x17,2
    006E 9AC2      SBI	0x18,2
    006F E001      LDI	R16,1
    0070 E010      LDI	R17,0
    0071 DFC5      RCALL	_delayus
    0072 9AB8      SBI	0x17,0
    0073 98C0      CBI	0x18,0
    0074 E001      LDI	R16,1
    0075 E010      LDI	R17,0
    0076 DFC0      RCALL	_delayus
    0077 9ABA      SBI	0x17,2
    0078 98C2      CBI	0x18,2
    0079 E001      LDI	R16,1
    007A E010      LDI	R17,0
    007B DFBB      RCALL	_delayus
    007C 9508      RET
(0075) }
(0076) void stop(void)
(0077) {
(0078)    sda0; delayus(1); scl1; delayus(1); sda1; delayus(1);
_stop:
    007D 9AB8      SBI	0x17,0
    007E 98C0      CBI	0x18,0
    007F E001      LDI	R16,1
    0080 E010      LDI	R17,0
    0081 DFB5      RCALL	_delayus
    0082 9ABA      SBI	0x17,2
    0083 9AC2      SBI	0x18,2
    0084 E001      LDI	R16,1
    0085 E010      LDI	R17,0
    0086 DFB0      RCALL	_delayus
    0087 9AB8      SBI	0x17,0
    0088 9AC0      SBI	0x18,0
    0089 E001      LDI	R16,1
    008A E010      LDI	R17,0
    008B DFAB      RCALL	_delayus
    008C 9508      RET
_writex:
  i                    --> R20
  temp                 --> R22
  j                    --> R20
    008D D1D8      RCALL	push_gset2
    008E 2F40      MOV	R20,R16
(0079) }
(0080) void writex(uchar j)
(0081) {
(0082)    uchar i,temp;
(0083)    temp=j;
    008F 2F64      MOV	R22,R20
(0084)    for (i=0;i<8;i++){
    0090 2744      CLR	R20
    0091 C016      RJMP	0x00A8
(0085)       scl0; delayus(1); 
    0092 9ABA      SBI	0x17,2
    0093 98C2      CBI	0x18,2
    0094 E001      LDI	R16,1
    0095 E010      LDI	R17,0
    0096 DFA0      RCALL	_delayus
(0086) 	  if((temp&0x80)==0){sda0;}
    0097 FD67      SBRC	R22,7
    0098 C003      RJMP	0x009C
    0099 9AB8      SBI	0x17,0
    009A 98C0      CBI	0x18,0
    009B C002      RJMP	0x009E
(0087) 	  else{sda1;}
    009C 9AB8      SBI	0x17,0
    009D 9AC0      SBI	0x18,0
(0088) 	  delayus(1); scl1; delayus(1);
    009E E001      LDI	R16,1
    009F E010      LDI	R17,0
    00A0 DF96      RCALL	_delayus
    00A1 9ABA      SBI	0x17,2
    00A2 9AC2      SBI	0x18,2
    00A3 E001      LDI	R16,1
    00A4 E010      LDI	R17,0
    00A5 DF91      RCALL	_delayus
(0089) 	  temp=temp<<1; 
    00A6 0F66      LSL	R22
    00A7 9543      INC	R20
    00A8 3048      CPI	R20,0x8
    00A9 F340      BCS	0x0092
(0090)    }
(0091)    scl0; delayus(1); sda1; delayus(1);
    00AA 9ABA      SBI	0x17,2
    00AB 98C2      CBI	0x18,2
    00AC E001      LDI	R16,1
    00AD E010      LDI	R17,0
    00AE DF88      RCALL	_delayus
    00AF 9AB8      SBI	0x17,0
    00B0 9AC0      SBI	0x18,0
    00B1 E001      LDI	R16,1
    00B2 E010      LDI	R17,0
    00B3 DF83      RCALL	_delayus
    00B4 D1A7      RCALL	pop_gset2
    00B5 9508      RET
_readx:
  j                    --> R20
  i                    --> R22
  k                    --> R10
    00B6 D1AD      RCALL	push_gset3
(0092) }
(0093) 
(0094) unsigned char readx(void)
(0095) {
(0096)    uchar i,j,k=0;
    00B7 24AA      CLR	R10
(0097)    scl0; delayus(1); sda1;
    00B8 9ABA      SBI	0x17,2
    00B9 98C2      CBI	0x18,2
    00BA E001      LDI	R16,1
    00BB E010      LDI	R17,0
    00BC DF7A      RCALL	_delayus
    00BD 9AB8      SBI	0x17,0
    00BE 9AC0      SBI	0x18,0
(0098)    for (i=0;i<8;i++){
    00BF 2766      CLR	R22
    00C0 C016      RJMP	0x00D7
(0099)       delayus(1); scl1; delayus(1);
    00C1 E001      LDI	R16,1
    00C2 E010      LDI	R17,0
    00C3 DF73      RCALL	_delayus
    00C4 9ABA      SBI	0x17,2
    00C5 9AC2      SBI	0x18,2
    00C6 E001      LDI	R16,1
    00C7 E010      LDI	R17,0
    00C8 DF6E      RCALL	_delayus
(0100) 	  sdawei;
    00C9 98B8      CBI	0x17,0
    00CA 9AC0      SBI	0x18,0
(0101)       if ((PINB&0X01)==0){j=0;}
    00CB 99B0      SBIC	0x16,0
    00CC C002      RJMP	0x00CF
    00CD 2744      CLR	R20
    00CE C001      RJMP	0x00D0
(0102)       else {j=1;}
    00CF E041      LDI	R20,1
(0103)       k=(k<<1)|j; scl0;
    00D0 2C2A      MOV	R2,R10
    00D1 0C22      LSL	R2
    00D2 2A24      OR	R2,R20
    00D3 2CA2      MOV	R10,R2
    00D4 9ABA      SBI	0x17,2
    00D5 98C2      CBI	0x18,2
    00D6 9563      INC	R22
    00D7 3068      CPI	R22,0x8
    00D8 F340      BCS	0x00C1
(0104)    }
(0105)    delayus(1); return(k);
    00D9 E001      LDI	R16,1
    00DA E010      LDI	R17,0
    00DB DF5B      RCALL	_delayus
    00DC 2D0A      MOV	R16,R10
    00DD D180      RCALL	pop_gset3
    00DE 9508      RET
_clock:
  i                    --> R20
    00DF D188      RCALL	push_gset1
(0106) }
(0107) 
(0108) void clock()
(0109) {
(0110)    uchar i=0;
    00E0 2744      CLR	R20
(0111)    scl1; delayus(1);
    00E1 9ABA      SBI	0x17,2
    00E2 9AC2      SBI	0x18,2
    00E3 E001      LDI	R16,1
    00E4 E010      LDI	R17,0
    00E5 DF51      RCALL	_delayus
(0112)    sdawei;
    00E6 98B8      CBI	0x17,0
    00E7 9AC0      SBI	0x18,0
    00E8 C003      RJMP	0x00EC
(0113)    while ((PINB&0X01!=0)&&(i<255)){i++;sdawei;}
    00E9 9543      INC	R20
    00EA 98B8      CBI	0x17,0
    00EB 9AC0      SBI	0x18,0
    00EC 9BB0      SBIS	0x16,0
    00ED C002      RJMP	0x00F0
    00EE 3F4F      CPI	R20,0xFF
    00EF F3C8      BCS	0x00E9
(0114)    scl0; delayus(1);
    00F0 9ABA      SBI	0x17,2
    00F1 98C2      CBI	0x18,2
    00F2 E001      LDI	R16,1
    00F3 E010      LDI	R17,0
    00F4 DF42      RCALL	_delayus
    00F5 D175      RCALL	pop_gset1
    00F6 9508      RET
_x24c02_read:
  i                    --> R20
  address              --> R20
    00F7 D170      RCALL	push_gset1
    00F8 2F40      MOV	R20,R16
(0115) }
(0116) uchar x24c02_read(uchar address)
(0117) {
(0118)    uchar i;
(0119)    start(); writex(0xa0);
    00F9 DF6E      RCALL	_start
    00FA EA00      LDI	R16,0xA0
    00FB DF91      RCALL	_writex
(0120)    clock(); writex(address);
    00FC DFE2      RCALL	_clock
    00FD 2F04      MOV	R16,R20
    00FE DF8E      RCALL	_writex
(0121)    clock(); start();
    00FF DFDF      RCALL	_clock
    0100 DF67      RCALL	_start
(0122)    writex(0xa1); clock();
    0101 EA01      LDI	R16,0xA1
    0102 DF8A      RCALL	_writex
    0103 DFDB      RCALL	_clock
(0123)    i=readx(); stop();
    0104 DFB1      RCALL	_readx
    0105 2F40      MOV	R20,R16
    0106 DF76      RCALL	_stop
(0124)    delayus(10);
    0107 E00A      LDI	R16,0xA
    0108 E010      LDI	R17,0
    0109 DF2D      RCALL	_delayus
(0125)    return(i);
    010A 2F04      MOV	R16,R20
    010B D15F      RCALL	pop_gset1
    010C 9508      RET
_x24c02_write:
  info                 --> R20
  address              --> R22
    010D D158      RCALL	push_gset2
    010E 2F42      MOV	R20,R18
    010F 2F60      MOV	R22,R16
(0126) }
(0127) void x24c02_write(uchar address,uchar info)
(0128) {  
(0129)    //CLI();
(0130)    start(); writex(0xa0);
    0110 DF57      RCALL	_start
    0111 EA00      LDI	R16,0xA0
    0112 DF7A      RCALL	_writex
(0131)    clock(); writex(address);
    0113 DFCB      RCALL	_clock
    0114 2F06      MOV	R16,R22
    0115 DF77      RCALL	_writex
(0132)    clock(); writex(info);
    0116 DFC8      RCALL	_clock
    0117 2F04      MOV	R16,R20
    0118 DF74      RCALL	_writex
(0133)    clock(); stop();
    0119 DFC5      RCALL	_clock
    011A DF62      RCALL	_stop
(0134)    delayus(50);
    011B E302      LDI	R16,0x32
    011C E010      LDI	R17,0
    011D DF19      RCALL	_delayus
    011E D13D      RCALL	pop_gset2
    011F 9508      RET
_jiancheicka:
  a                    --> R20
    0120 D145      RCALL	push_gset2
(0135)    //SEI();
(0136) }
(0137)    
(0138) void jiancheicka(void)
(0139) {
(0140)   uchar a=0;
    0121 2744      CLR	R20
(0141)  DDRB&=~(1<<5);
    0122 98BD      CBI	0x17,5
(0142)  PORTB|=(1<<5);
    0123 9AC5      SBI	0x18,5
(0143)   if(((PINB&0X20)==0)&(kawei==1))
    0124 99B5      SBIC	0x16,5
    0125 C003      RJMP	0x0129
    0126 E061      LDI	R22,1
    0127 E070      LDI	R23,0
    0128 C002      RJMP	0x012B
    0129 2766      CLR	R22
    012A 2777      CLR	R23
    012B 91800073  LDS	R24,kawei
    012D 3081      CPI	R24,1
    012E F419      BNE	0x0132
    012F E041      LDI	R20,1
    0130 E050      LDI	R21,0