📄 8x8multiplier.sp
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.vec sim_multipilier8x8_10.vect
.lib '../spice_model/cmos25_level49.lib' TT
.global vdd vss
.param vsupply=2.5 vm='vsupply/2' vl='vsupply*.1' vh='vsupply*.9' period=20
.tran 'period*0.005*1n' 'period*10*1n'
.option post
vdd vdd 0 vsupply
c1 p1 0 1p
c2 p2 0 1p
c3 p3 0 1p
c4 p4 0 1p
c5 p5 0 1p
c6 p6 0 1p
c7 p7 0 1p
c8 p8 0 1p
c9 p9 0 1p
c10 p10 0 1p
c11 p11 0 1p
c12 p12 0 1p
c13 p13 0 1p
c14 p14 0 1p
c15 p15 0 1p
c16 p16 0 1p
********************************************
*** describe here the half_adder ***
********************************************
** input A B
** output S Co
********************************************
.subckt half_adder A B S Co M=1
mp1 1 A vdd vdd pmos l=0.25u w='0.25u*4*M'
mp2 1 B vdd vdd pmos l=0.25u w='0.25u*4*M'
mp3 Co 1 vdd vdd pmos l=0.25u w='0.25u*4*M'
mp4 4 1 vdd vdd pmos l=0.25u w='0.25u*4*M'
mp5 3 A vdd vdd pmos l=0.25u w='0.25u*4*M'
mp6 4 B 3 vdd pmos l=0.25u w='0.25u*4*M'
mp7 S 4 vdd vdd pmos l=0.25u w='0.25u*4*M'
mn1 1 A 2 0 nmos l=0.25u w='0.25u*2*M'
mn2 2 B 0 0 nmos l=0.25u w='0.25u*2*M'
mn3 Co 1 0 0 nmos l=0.25u w='0.25u*2*M'
mn4 4 1 5 0 nmos l=0.25u w='0.25u*2*M'
mn5 5 A 0 0 nmos l=0.25u w='0.25u*2*M'
mn6 5 B 0 0 nmos l=0.25u w='0.25u*2*M'
mn7 S 4 0 0 nmos l=0.25u w='0.25u*2*M'
.ends half_adder
********************************************
*** describe here the full_adder ***
********************************************
** input A B Ci
** output S Co
********************************************
.subckt full_adder A B Ci S Co M=1
M1 1 A vdd vdd pmos l=0.25u w='0.25u*4*M'
M2 2 B 1 vdd PMOS l=0.25u w='0.25u*4*M'
M3 X A 2 vdd PMOS l=0.25u w='0.25u*4*M'
M4 X Ci 3 0 NMOS l=0.25u w='0.25u*2*M'
M5 3 A 0 0 NMOS l=0.25u w='0.25u*2*M'
M6 3 B 0 0 NMOS l=0.25u w='0.25u*2*M'
M7 1 B vdd vdd PMOS l=0.25u w='0.25u*4*M'
M8 X Ci 1 vdd PMOS l=0.25u w='0.25u*4*M'
M9 X A 4 0 NMOS l=0.25u w='0.25u*2*M'
M10 4 B 0 0 NMOS l=0.25u w='0.25u*2*M'
M11 Co X vdd vdd PMOS l=0.25u w='0.25u*4*M'
M12 Co X 0 0 NMOS l=0.25u w='0.25u*2*M'
M13 5 Ci vdd vdd PMOS l=0.25u w='0.25u*4*M'
M14 5 A vdd vdd PMOS l=0.25u w='0.25u*4*M'
M15 5 B vdd vdd PMOS l=0.25u w='0.25u*4*M'
M16 8 X 5 vdd PMOS l=0.25u w='0.25u*4*M'
M17 6 A 5 vdd PMOS l=0.25u w='0.25u*4*M'
M18 7 B 6 vdd PMOS l=0.25u w='0.25u*4*M'
M19 8 Ci 7 vdd PMOS l=0.25u w='0.25u*4*M'
M20 8 X 9 0 NMOS l=0.25u w='0.25u*2*M'
M21 9 A 0 0 NMOS l=0.25u w='0.25u*2*M'
M22 9 B 0 0 NMOS l=0.25u w='0.25u*2*M'
M23 9 Ci 0 0 NMOS l=0.25u w='0.25u*2*M'
M24 8 Ci 10 0 NMOS l=0.25u w='0.25u*2*M'
M25 10 A 11 0 NMOS l=0.25u w='0.25u*2*M'
M26 11 B 0 0 NMOS l=0.25u w='0.25u*2*M'
M27 S 8 vdd vdd PMOS l=0.25u w='0.25u*4*M'
M28 S 8 0 0 NMOS l=0.25u w='0.25u*2*M'
.ends full_adder
********************************************
*** describe here the BoothCoing ***
********************************************
** input A B C
** output Yi Y2i Mi
********************************************
.subckt BoothCoding A B C Mi Y2i Yi M=4
mp1 1 C vdd vdd pmos l=0.25u w='0.25u*4*M'
mp2 1 B vdd vdd pmos l=0.25u w='0.25u*4*M'
mp3 4 1 vdd vdd pmos l=0.25u w='0.25u*4*M'
mp4 3 C vdd vdd pmos l=0.25u w='0.25u*4*M'
mp5 4 B 3 vdd pmos l=0.25u w='0.25u*4*M'
mp6 Yi 4 vdd vdd pmos l=0.25u w='0.25u*4*M'
mp7 C_ C vdd vdd pmos l=0.25u w='0.25u*4*M'
mp8 B_ B vdd vdd pmos l=0.25u w='0.25u*4*M'
mp9 A_ A vdd vdd pmos l=0.25u w='0.25u*4*M'
mp10 6 C vdd vdd pmos l=0.25u w='0.25u*4*M'
mp11 6 B vdd vdd pmos l=0.25u w='0.25u*4*M'
mp12 6 A_ vdd vdd pmos l=0.25u w='0.25u*4*M'
mp13 9 C_ vdd vdd pmos l=0.25u w='0.25u*4*M'
mp14 9 B_ vdd vdd pmos l=0.25u w='0.25u*4*M'
mp15 9 A vdd vdd pmos l=0.25u w='0.25u*4*M'
mp16 Y2i 6 vdd vdd pmos l=0.25u w='0.25u*4*M'
mp17 Y2i 9 vdd vdd pmos l=0.25u w='0.25u*4*M'
mp18 Mi A_ vdd vdd pmos l=0.25u w='0.25u*4*M'
mn1 1 C 2 0 nmos l=0.25u w='0.25u*2*M'
mn2 2 B 0 0 nmos l=0.25u w='0.25u*2*M'
mn3 4 1 5 0 nmos l=0.25u w='0.25u*2*M'
mn4 5 C 0 0 nmos l=0.25u w='0.25u*2*M'
mn5 5 B 0 0 nmos l=0.25u w='0.25u*2*M'
mn6 Yi 4 0 0 nmos l=0.25u w='0.25u*2*M'
mn7 C_ C 0 0 nmos l=0.25u w='0.25u*2*M'
mn8 B_ B 0 0 nmos l=0.25u w='0.25u*2*M'
mn9 A_ A 0 0 nmos l=0.25u w='0.25u*2*M'
mn10 8 C 0 0 nmos l=0.25u w='0.25u*2*M'
mn11 7 B 8 0 nmos l=0.25u w='0.25u*2*M'
mn12 6 A_ 7 0 nmos l=0.25u w='0.25u*2*M'
mn13 9 C_ 10 0 nmos l=0.25u w='0.25u*2*M'
mn14 10 B_ 11 0 nmos l=0.25u w='0.25u*2*M'
mn15 11 A 0 0 nmos l=0.25u w='0.25u*2*M'
mn16 Y2i 6 12 0 nmos l=0.25u w='0.25u*2*M'
mn17 12 9 0 0 nmos l=0.25u w='0.25u*2*M'
mn18 Mi A_ 0 0 nmos l=0.25u w='0.25u*2*M'
.ends BoothCoding
********************************************
*** describe here the BoothSelector ***
********************************************
*The output is PPij
*The input is Yi Yj Yj-1 Y2i Mi
*******************************************
.subckt BoothSelector Yj Yj-1 Yi Y2i Mi PPij M=2
mp1 1 Yi vdd vdd pmos l=0.25u w='0.25u*4*M'
mp2 1 Yj vdd vdd pmos l=0.25u w='0.25u*4*M'
mp3 Q Yj-1 1 vdd pmos l=0.25u w='0.25u*4*M'
mp4 Q Y2i 1 vdd pmos l=0.25u w='0.25u*4*M'
mp5 6 Q vdd vdd pmos l=0.25u w='0.25u*4*M'
mp6 6 Mi vdd vdd pmos l=0.25u w='0.25u*4*M'
mp7 PPij 6 vdd vdd pmos l=0.25u w='0.25u*4*M'
mp8 7 Q vdd vdd pmos l=0.25u w='0.25u*4*M'
mp9 PPij Mi 7 vdd pmos l=0.25u w='0.25u*4*M'
mn1 Q Yi 3 0 nmos l=0.25u w='0.25u*2*M'
mn2 Q Yj-1 4 0 nmos l=0.25u w='0.25u*2*M'
mn3 3 Yj 0 0 nmos l=0.25u w='0.25u*2*M'
mn4 4 Y2i 0 0 nmos l=0.25u w='0.25u*2*M'
mn5 6 Q 5 0 nmos l=0.25u w='0.25u*2*M'
mn6 5 Mi 0 0 nmos l=0.25u w='0.25u*2*M'
mn7 PPij 6 8 0 nmos l=0.25u w='0.25u*2*M'
mn8 8 Q 0 0 nmos l=0.25u w='0.25u*2*M'
mn9 8 Mi 0 0 nmos l=0.25u w='0.25u*2*M'
.ends BoothSelector
.subckt not A A_ M=1
mp1 A_ A vdd vdd pmos l=0.25u w='0.25u*4*M'
mn1 A_ A 0 0 nmos l=0.25u w='0.25u*2*M'
.ends not
.subckt buffer x x_buff M=1 N=3
xnot1 x x_ not M=1
xnot2 x_ x_buff not N=1
.ends buffer
**########################################**
*** 8x8 multiplier design ***
**########################################**
*.subckt multipilier_10 a[8:1] b[8:1] p[16:1]
****a[8:1]->a_f[8:1]
****b[8:1]->b_f[8:1]
****p_f[16:1]->p[16:1]
xbuffer1 a1 a1_f buffer M=1 N=4
xbuffer2 a2 a2_f buffer M=1 N=4
xbuffer3 a3 a3_f buffer M=1 N=4
xbuffer4 a4 a4_f buffer M=1 N=4
xbuffer5 a5 a5_f buffer M=1 N=4
xbuffer6 a6 a6_f buffer M=1 N=4
xbuffer7 a7 a7_f buffer M=1 N=4
xbuffer8 a8 a8_f buffer M=1 N=4
xbuffer10 b1 b1_f buffer M=1 N=4
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