📄 mpc860.h
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/* Ethernet parameter RAM (SCC) */
/*-------------------------------------------------------------------------*/
struct ethernet_pram
{
/*--------------------*/
/* SCC parameter RAM */
/*--------------------*/
UHWORD rbase; /* RX BD base address */
UHWORD tbase; /* TX BD base address */
UBYTE rfcr; /* Rx function code */
UBYTE tfcr; /* Tx function code */
UHWORD mrblr; /* Rx buffer length */
UWORD rstate; /* Rx internal state */
UWORD rptr; /* Rx internal data pointer */
UHWORD rbptr; /* rb BD Pointer */
UHWORD rcount; /* Rx internal byte count */
UWORD rtemp; /* Rx temp */
UWORD tstate; /* Tx internal state */
UWORD tptr; /* Tx internal data pointer */
UHWORD tbptr; /* Tx BD pointer */
UHWORD tcount; /* Tx byte count */
UWORD ttemp; /* Tx temp */
UWORD rcrc; /* temp receive CRC */
UWORD tcrc; /* temp transmit CRC */
/*---------------------------------*/
/* ETHERNET specific parameter RAM */
/*---------------------------------*/
UWORD c_pres; /* preset CRC */
UWORD c_mask; /* constant mask for CRC */
UWORD crcec; /* CRC error counter */
UWORD alec; /* alighnment error counter */
UWORD disfc; /* discard frame counter */
UHWORD pads; /* short frame PAD characters */
UHWORD ret_lim; /* retry limit threshold */
UHWORD ret_cnt; /* retry limit counter */
UHWORD mflr; /* maximum frame length reg */
UHWORD minflr; /* minimum frame length reg */
UHWORD maxd1; /* maximum DMA1 length reg */
UHWORD maxd2; /* maximum DMA2 length reg */
UHWORD maxd; /* rx max DMA */
UHWORD dma_cnt; /* rx dma counter */
UHWORD max_b; /* max bd byte count */
UHWORD gaddr1; /* group address filter 1 */
UHWORD gaddr2; /* group address filter 2 */
UHWORD gaddr3; /* group address filter 3 */
UHWORD gaddr4; /* group address filter 4 */
UWORD tbuf0_data0; /* save area 0 - current frm */
UWORD tbuf0_data1; /* save area 1 - current frm */
UWORD tbuf0_rba0;
UWORD tbuf0_crc;
UHWORD tbuf0_bcnt;
UHWORD paddr_h; /* physical address (MSB) */
UHWORD paddr_m; /* physical address */
UHWORD paddr_l; /* physical address (LSB) */
UHWORD p_per; /* persistence */
UHWORD rfbd_ptr; /* rx first bd pointer */
UHWORD tfbd_ptr; /* tx first bd pointer */
UHWORD tlbd_ptr; /* tx last bd pointer */
UWORD tbuf1_data0; /* save area 0 - next frame */
UWORD tbuf1_data1; /* save area 1 - next frame */
UWORD tbuf1_rba0;
UWORD tbuf1_crc;
UHWORD tbuf1_bcnt;
UHWORD tx_len; /* tx frame length counter */
UHWORD iaddr1; /* individual address filter 1*/
UHWORD iaddr2; /* individual address filter 2*/
UHWORD iaddr3; /* individual address filter 3*/
UHWORD iaddr4; /* individual address filter 4*/
UHWORD boff_cnt; /* back-off counter */
UHWORD taddr_h; /* temp address (MSB) */
UHWORD taddr_m; /* temp address */
UHWORD taddr_l; /* temp address (LSB) */
};
/*------------------------------------------------------------------*/
/* QMC definitions */
/*------------------------------------------------------------------*/
struct global_qmc_pram {
UWORD mcbase; /* Multichannel Base pointer */
UHWORD qmcstate; /* Multichannel Controller state */
UHWORD mrblr; /* Maximum Receive Buffer Length */
UHWORD tx_s_ptr; /* TSATTx Pointer */
UHWORD rxptr; /* Current Time slot entry in TSATRx */
UHWORD grfthr; /* Global Receive frame threshold */
UHWORD grfcnt; /* Global Receive Frame Count */
UWORD intbase; /* Multichannel Base address */
UWORD intptr; /* Pointer to interrupt queue */
UHWORD rx_s_ptr; /* TSATRx Pointer */
UHWORD txptr; /* Current Time slot entry in TSATTx */
UWORD c_mask32; /* CRC Constant (debb20e3) */
UHWORD tsatrx[32]; /* Time Slot Assignment Table Rx */
UHWORD tsattx[32]; /* Time Slot Assignment Table Tx */
UHWORD c_mask16; /* CRC Constant (f0b8) */
};
/*------------------------------------------*/
/* QMC HDLC channel specific parameter RAM */
/*------------------------------------------*/
struct qmc_hdlc_pram {
UHWORD tbase; /* Tx Buffer Descriptors Base Address */
UHWORD chamr; /* Channel Mode Register */
UWORD tstate; /* Tx Internal State */
UWORD txintr; /* Tx Internal Data Pointer */
UHWORD tbptr; /* Tx Buffer Descriptor Pointer */
UHWORD txcntr; /* Tx Internal Byte Count */
UWORD tupack; /* (Tx Temp) */
UWORD zistate; /* Zero Insertion machine state */
UWORD tcrc; /* Temp Transmit CRC */
UHWORD intmsk; /* Channel's interrupt mask flags */
UHWORD bdflags;
UHWORD rbase; /* Rx Buffer Descriptors Base Address */
UHWORD mflr; /* Max Frame Length Register */
UWORD rstate; /* Rx Internal State */
UWORD rxintr; /* Rx Internal Data Pointer */
UHWORD rbptr; /* Rx Buffer Descriptor Pointer */
UHWORD rxbyc; /* Rx Internal Byte Count */
UWORD rpack; /* (Rx Temp) */
UWORD zdstate; /* Zero Deletion machine state */
UWORD rcrc; /* Temp Transmit CRC */
UHWORD maxc; /* Max_length counter */
UHWORD tmp_mb; /* Temp */
};
/*-------------------------------------------------*/
/* QMC Transparent channel specific parameter RAM */
/*-------------------------------------------------*/
struct qmc_tran_pram {
UHWORD tbase; /* Tx Bufer Descriptors Base Address */
UHWORD chamr; /* Channel Mode Register */
UWORD tstate; /* Tx Internal State */
UWORD txintr; /* Tx Internal Data Pointer */
UHWORD tbptr; /* Tx Buffer Descriptor Pointer */
UHWORD txcntr; /* Tx Internal Byte Count */
UWORD tupack; /* (Tx Temp) */
UWORD zistate; /* Zero Insertion machine state */
UWORD RESERVED8;
UHWORD intmsk; /* Channel's interrupt mask flags */
UHWORD bdflags;
UHWORD rbase; /* Rx Buffer Descriptors Base Address */
UHWORD tmrblr; /* Max receive buffer length */
UWORD rstate; /* Rx Internal State */
UWORD rxintr; /* Rx Internal Data Pointer */
UHWORD rbptr; /* Rx Buffer Descriptor Pointer */
UHWORD rxbyc; /* Rx Internal Byte Count */
UWORD rpack; /* (Rx Temp) */
UWORD zdstate; /* Zero Deletion machine state */
UWORD RESERVED9; /* Temp Transmit CRC */
UHWORD trnsync; /* Max_length counter */
UHWORD RESERVED10; /* Temp */
};
/*----------------------------------------------------------*/
/* allows multiprotocol array declaration in the memory map */
/*----------------------------------------------------------*/
struct qmc_chan_pram
{
union
{
struct qmc_hdlc_pram h;
struct qmc_tran_pram t;
}h_or_t;
};
/*--------------------------------------------------------------------*/
/* SMC UART parameter RAM */
/*--------------------------------------------------------------------*/
struct smc_uart_pram
{
UHWORD rbase; /* Rx BD Base Address */
UHWORD tbase; /* Tx BD Base Address */
UBYTE rfcr; /* Rx function code */
UBYTE tfcr; /* Tx function code */
UHWORD mrblr; /* Rx buffer length */
UWORD rstate; /* Rx internal state */
UWORD rptr; /* Rx internal data pointer */
UHWORD rbptr; /* rb BD Pointer */
UHWORD rcount; /* Rx internal byte count */
UWORD rtemp; /* Rx temp */
UWORD tstate; /* Tx internal state */
UWORD tptr; /* Tx internal data pointer */
UHWORD tbptr; /* Tx BD pointer */
UHWORD tcount; /* Tx byte count */
UWORD ttemp; /* Tx temp */
UHWORD max_idl; /* Maximum IDLE Characters */
UHWORD idlc; /* Temporary IDLE Counter */
UHWORD brkln; /* Last Rx Break Length */
UHWORD brkec; /* Rx Break Condition Counter */
UHWORD brkcr; /* Break Count Register (Tx) */
UHWORD r_mask; /* Temporary bit mask */
};
/*--------------------------------------------------------------------------*/
/* SMC Transparent mode parameter RAM */
/*--------------------------------------------------------------------------*/
struct smc_trnsp_pram
{
UHWORD rbase; /* Rx BD Base Address */
UHWORD tbase; /* Tx BD Base Address */
UBYTE rfcr; /* Rx function code */
UBYTE tfcr; /* Tx function code */
UHWORD mrblr; /* Rx buffer length */
UWORD rstate; /* Rx internal state */
UWORD rptr; /* Rx internal data pointer */
UHWORD rbptr; /* rb BD Pointer */
UHWORD rcount; /* Rx internal byte count */
UWORD rtemp; /* Rx temp */
UWORD tstate; /* Tx internal state */
UWORD tptr; /* Tx internal data pointer */
UHWORD tbptr; /* Tx BD pointer */
UHWORD tcount; /* Tx byte count */
UWORD ttemp; /* Tx temp */
UHWORD RESERVED11[5]; /* Reserved */
};
/*--------------------------------------------------------------------------*/
/* SPI parameter RAM */
/*--------------------------------------------------------------------------*/
#define SPI_R 0x8000 /* Ready bit in BD */
struct spi_pram
{
UHWORD rbase; /* Rx BD Base Address */
UHWORD tbase; /* Tx BD Base Address */
UBYTE rfcr; /* Rx function code */
UBYTE tfcr; /* Tx function code */
UHWORD mrblr; /* Rx buffer length */
UWORD rstate; /* Rx internal state */
UWORD rptr; /* Rx internal data pointer */
UHWORD rbptr; /* rb BD Pointer */
UHWORD rcount; /* Rx internal byte count */
UWORD rtemp; /* Rx temp */
UWORD tstate; /* Tx internal state */
UWORD tptr; /* Tx internal data pointer */
UHWORD tbptr; /* Tx BD pointer */
UHWORD tcount; /* Tx byte count */
UWORD ttemp; /* Tx temp */
};
/*--------------------------------------------------------------------------*/
/* I2C parameter RAM */
/*--------------------------------------------------------------------------*/
struct i2c_pram
{
/*--------------------*/
/* I2C parameter RAM */
/*--------------------*/
UHWORD rbase; /* RX BD base address */
UHWORD tbase; /* TX BD base address */
UBYTE rfcr; /* Rx function code */
UBYTE tfcr; /* Tx function code */
UHWORD mrblr; /* Rx buffer length */
UWORD rstate; /* Rx internal state */
UWORD rptr; /* Rx internal data pointer */
UHWORD rbptr; /* rb BD Pointer */
UHWORD rcount; /* Rx internal byte count */
UWORD rtemp; /* Rx temp */
UWORD tstate; /* Tx internal state */
UWORD tptr; /* Tx internal data pointer */
UHWORD tbptr; /* Tx BD pointer */
UHWORD tcount; /* Tx byte count */
UWORD ttemp; /* Tx temp */
};
/*--------------------------------------------------------------------------*/
/* PIP Centronics parameter RAM */
/*--------------------------------------------------------------------------*/
struct centronics_pram
{
UHWORD rbase; /* Rx BD Base Address */
UHWORD tbase; /* Tx BD Base Address */
UBYTE fcr; /* function code */
UBYTE smask; /* Status Mask */
UHWORD mrblr; /* Rx buffer length */
UWORD rstate; /* Rx internal state */
UWORD rptr; /* Rx internal data pointer */
UHWORD rbptr; /* rb BD Pointer */
UHWORD rcount; /* Rx internal byte count */
UWORD rtemp; /* Rx temp */
UWORD tstate; /* Tx internal state */
UWORD tptr; /* Tx internal data pointer */
UHWORD tbptr; /* Tx BD pointer */
UHWORD tcount; /* Tx byte count */
UWORD ttemp; /* Tx temp */
UHWORD max_sl; /* Maximum Silence period */
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