init.c

基于mcf5307开发板的sed1335控制液晶屏显示的程序

        /************************************************************************/
        /************************************************************************/
        /*  ChipSelect 0 - Boot FLASH 28F800                                    */
        /*                                                                      */
        /*  ChipSelect 0 is the global chip select coming out of system reset.  */
        /*  CS0 is asserted for every access until CSMR0 is written.            */
        /*  Therefore, the entire ChipSelect must be properly set prior to      */
        /*  asserting CSCR0_V.                                                  */
        /************************************************************************/
        imm->cs.CSAR0 = 0xff00;                       // CS0-flash U7
        imm->cs.CSCR0 = ( 0
                | MCF5307_CS_CSCR_WS(10)
                | MCF5307_CS_CSCR_AA    
                | MCF5307_CS_CSCR_PS_16) ;  
        imm->cs.CSMR0 = ( 0
                | MCF5307_CS_CSMR_MASK_8M
                | MCF5307_CS_CSMR_V ) ;
 
	
	
        /************************************************************************/
        /*  ChipSelect 1 - Flash-Memory                                         */
        /***********************************7*************************************/
	imm->cs.CSAR1 = 0xfe00;                       // CS1-flash U8
        imm->cs.CSCR1 = ( 0
                | MCF5307_CS_CSCR_WS(10)
                | MCF5307_CS_CSCR_AA    
                | MCF5307_CS_CSCR_PS_16 ) ;
        imm->cs.CSMR1 = ( 0
                | MCF5307_CS_CSMR_MASK_8M
                | MCF5307_CS_CSMR_V ) ;
        
        
                
        /************************************************************************/
        /*  ChipSelect 2                                                        */
        /*  CPLD & Super I/O 
        /************************************************************************/
	imm->cs.CSAR2 = 0x2200;
        imm->cs.CSCR2 = ( 0
		| MCF5307_CS_CSCR_WS(15)
                | MCF5307_CS_CSCR_AA    
	        | MCF5307_CS_CSCR_PS_16 ) ;
        imm->cs.CSMR2 = ( 0
                | MCF5307_CS_CSMR_MASK_16M
                | MCF5307_CS_CSMR_V ) ;
                
        
        
                
        /************************************************************************/
        /*  ChipSelect 3                                                        */
        /*  EtherNet Address
        /************************************************************************/
	imm->cs.CSAR3 = 0x4400;
        imm->cs.CSCR3 = ( 0
	  	| MCF5307_CS_CSCR_WS(4)
                | MCF5307_CS_CSCR_AA
                | MCF5307_CS_CSCR_BEM	    
                | MCF5307_CS_CSCR_PS_16 ) ;
        imm->cs.CSMR3 = ( 0
                | MCF5307_CS_CSMR_MASK_8M
                | MCF5307_CS_CSMR_V ) ;
        
        
         
        /************************************************************************/
        /*  ChipSelect 4                                                        */
        /*  Cineloop Memory
        /************************************************************************/
        imm->cs.CSAR4 = 0x5500;
	imm->cs.CSCR4 = ( 0
		| MCF5307_CS_CSCR_WS(15)
            //    | MCF5307_CS_CSCR_AA 			//----Now use Ta by FPGA U31
                | MCF5307_CS_CSCR_BEM	   
	        | MCF5307_CS_CSCR_PS_16 ) ;
	imm->cs.CSMR4 = ( 0
		| MCF5307_CS_CSMR_MASK_16M
                | MCF5307_CS_CSMR_V ) ;
        
        
                
        /************************************************************************/
        /*  ChipSelect 5                                                        */
        /*  Cineloop Graphic Ram & Image Ram & Others
        /************************************************************************/
        imm->cs.CSAR5 = 0x6600;
        imm->cs.CSCR5 =(0
        	| MCF5307_CS_CSCR_WS(8)
                | MCF5307_CS_CSCR_AA
                | MCF5307_CS_CSCR_BEM	
	        | MCF5307_CS_CSCR_PS_16);
	imm->cs.CSMR5 =(0 
	        | MCF5307_CS_CSMR_MASK_16M
                | MCF5307_CS_CSMR_V ) ;
	
	
	
        /************************************************************************/
        /*  ChipSelect 6  
        /*  FeBus                                                               */
        /************************************************************************/
        imm->cs.CSAR6 = 0x7700;
	imm->cs.CSCR6 =(0
		| MCF5307_CS_CSCR_WS(10)  
		| MCF5307_CS_CSCR_AA 
		| MCF5307_CS_CSCR_PS_16) ;
        imm->cs.CSMR6 = ( 0
		| MCF5307_CS_CSMR_MASK_16M
                | MCF5307_CS_CSMR_V ) ;
        
        
        
        /************************************************************************/
        /*  ChipSelect 7 
        /*  Hard Disk                                             */
        /************************************************************************/
        imm->cs.CSAR7 = 0x8800;
	imm->cs.CSCR7 = ( 0
		| MCF5307_CS_CSCR_WS(15)
                | MCF5307_CS_CSCR_AA    
                | MCF5307_CS_CSCR_PS_16 ) ;
        imm->cs.CSMR7 = ( 0
		| MCF5307_CS_CSMR_MASK_8M
                | MCF5307_CS_CSMR_V ) ;
                
	
}  


/*************************************************************/
void
mcf5307_sdramc_init1 (MCF5307_IMM *imm)
{
	/*******************************************************
	* This routine is the first half of the SDRAM Controller
	* initialization.  It sets up all of the configuration
	* information.  We need time for eight refreshes
	* between this program and the second half of the init.
	*******************************************************/

	NATURAL32 junk = 0xA5A59696;
	/********************************************************
	* DRAM Controller Refresh Register calculation:
	*
	* # of bus clocks = (RC + 1) * 16
	* (703.83 bus clocks / 16) - 1 = RC
	* RC = 42.99 = 42 = 0x2A
	********************************************************/

	/* Initialize DRAM Registers: DCR, DACR, DMR */
	imm->dramc.DCR = 0x822A;                       //1000,0010,0010,1010   SDRAM,
	imm->dramc.DACR0 = 0x00001400;            //Base address00000,Refresh disenable because registers are being set up at this time.,32-bit总线
	imm->dramc.DCMR0 = 0x00FC0001;
	/*
	imm->dramc.DACR1 = 0x00001400;
	imm->dramc.DCMR1 = 0x00FC0001;
	*/

	/* Set IP (bit 3) in DACR */
	imm->dramc.DACR0 = 0x00001408;

	/*
	imm->dramc.DACR1 = 0x00001408;
	*/
	
	/* Write to each bank to initiate precharge */
	
	*(NATURAL32 *)0x00000400 = junk;
	
	/*(NATURAL32 *)0x01000400 = junk;*/
	
	/* Set RE (bit 15) in DACR */
	imm->dramc.DACR0 = 0x00009400;                 //寄存器设置完毕,此处使能SDRAM自动刷新功能
	imm->dramc.DACR1 = 0x01001400;
	imm->dramc.DCMR1 = 0x00FC0000;
	
}
/****************************************************************/
void
mcf5307_sdramc_init2 (MCF5307_IMM *imm)
{
	/********************************************************
	* This second half of the SDRAM Controller initialization
	* finishes the configuration.
	********************************************************/
	
	NATURAL32 junk = 0xA5A59696;
	

	/* Write to the SDRAM Mode Register (see UM pg. 11-34) */

	/* Finish the configuration by issuing the IMRS. */
	imm->dramc.DACR0 = 0x00009440;
	
	/*
	imm->dramc.DACR1 = 0x00009440;
	*/
	
	*(NATURAL32 *)0x00000400 = junk;
	
	/*
	*(NATURAL32 *)0x01000400 = junk;	
	*/
}


void ReInitSdram(MCF5307_IMM *imm)
{
 int i;
 mcf5307_sdramc_init1(imm);
 for(i=10000;i>0;i--)
 {
  ;	
 }	
 mcf5307_sdramc_init2(imm);	
}