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📄 readme.txt

📁 huffman code vhdl program
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**********************************************************************
** Disclaimer: LIMITED WARRANTY AND DISCLAMER. These designs are
**                     provided to you "as is". Xilinx and its licensors make and you
**                     receive no warranties or conditions, express, implied,
**                     statutory or otherwise, and Xilinx specifically disclaims any
**                     implied warranties of merchantability, non-infringement,or
**                     fitness for a particular purpose. Xilinx does not warrant that
**                     the functions contained in these designs will meet your
**                     requirements, or that the operation of these designs will be
**                     uninterrupted or error free, or that defects in the Designs
**                     will be corrected. Furthermore, Xilinx does not warrantor
**                     make any representations regarding use or the results of the
**                     use of the designs in terms of correctness, accuracy,
**                     reliability, or otherwise.
**
**                     LIMITATION OF LIABILITY. In no event will Xilinx or its
**                     licensors be liable for any loss of data, lost profits,cost
**                     or procurement of substitute goods or services, or for any
**                     special, incidental, consequential, or indirect damages
**                     arising from the use or operation of the designs or
**                     accompanying documentation, however caused and on any theory
**                     of liability. This limitation will apply even if Xilinx
**                     has been advised of the possibility of such damage. This
**                     limitation shall apply not-withstanding the failure of the
**                     essential purpose of any limited remedies herein.
**  
**  Copyright (c) 2003 Xilinx, Inc.
**  All rights reserved
**
******************************************************************************


XAPP616.zip file contains 

The word document
Verilog files (*.v)
    huffman_en_full.v
Vhdl file (*.vhd)
    huffman_en_full.vhd


The Verilog and VHDL synthesized and places and routed using Foundation 5.1.03i.
Synplify ProVerilog was used for synthesis.

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