📄 div.tan.rpt
字号:
Classic Timing Analyzer report for div
Wed Apr 01 08:37:38 2009
Quartus II Version 7.0 Build 33 02/05/2007 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'clk'
6. tco
7. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+------------------------------------------------+----------+----------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+----------+----------+------------+----------+--------------+
; Worst-case tco ; N/A ; None ; 6.854 ns ; q~reg0 ; q ; clk ; -- ; 0 ;
; Clock Setup: 'clk' ; N/A ; None ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; count[2] ; count[2] ; clk ; clk ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+------------------------------------------------+----------+----------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EPM240F100C5 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk' ;
+-------+------------------------------------------------+----------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+----------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; count[3] ; count[3] ; clk ; clk ; None ; None ; 2.381 ns ;
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; count[2] ; count[2] ; clk ; clk ; None ; None ; 2.381 ns ;
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; count[1] ; count[2] ; clk ; clk ; None ; None ; 2.192 ns ;
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; count[1] ; count[3] ; clk ; clk ; None ; None ; 2.191 ns ;
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; count[1] ; q~reg0 ; clk ; clk ; None ; None ; 2.184 ns ;
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; count[1] ; count[1] ; clk ; clk ; None ; None ; 2.181 ns ;
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; count[3] ; count[0] ; clk ; clk ; None ; None ; 2.170 ns ;
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; count[0] ; count[2] ; clk ; clk ; None ; None ; 2.145 ns ;
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; count[0] ; count[1] ; clk ; clk ; None ; None ; 2.013 ns ;
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; count[0] ; q~reg0 ; clk ; clk ; None ; None ; 2.012 ns ;
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; count[0] ; count[0] ; clk ; clk ; None ; None ; 2.008 ns ;
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; count[2] ; q~reg0 ; clk ; clk ; None ; None ; 1.790 ns ;
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; count[2] ; count[0] ; clk ; clk ; None ; None ; 1.787 ns ;
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; count[2] ; count[3] ; clk ; clk ; None ; None ; 1.785 ns ;
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; count[1] ; count[0] ; clk ; clk ; None ; None ; 1.611 ns ;
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; count[3] ; count[1] ; clk ; clk ; None ; None ; 1.597 ns ;
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; count[3] ; q~reg0 ; clk ; clk ; None ; None ; 1.596 ns ;
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; count[3] ; count[2] ; clk ; clk ; None ; None ; 1.592 ns ;
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; count[0] ; count[3] ; clk ; clk ; None ; None ; 1.539 ns ;
+-------+------------------------------------------------+----------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+
+--------------------------------------------------------------+
; tco ;
+-------+--------------+------------+--------+----+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+--------+----+------------+
; N/A ; None ; 6.854 ns ; q~reg0 ; q ; clk ;
+-------+--------------+------------+--------+----+------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
Info: Processing started: Wed Apr 01 08:37:38 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off div -c div
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 304.04 MHz between source register "count[3]" and destination register "count[3]"
Info: fmax restricted to clock pin edge rate 3.289 ns. Expand message to see actual delay path.
Info: + Longest register to register delay is 2.381 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y4_N8; Fanout = 5; REG Node = 'count[3]'
Info: 2: + IC(1.320 ns) + CELL(1.061 ns) = 2.381 ns; Loc. = LC_X2_Y4_N8; Fanout = 5; REG Node = 'count[3]'
Info: Total cell delay = 1.061 ns ( 44.56 % )
Info: Total interconnect delay = 1.320 ns ( 55.44 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "clk" to destination register is 3.348 ns
Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_E1; Fanout = 5; CLK Node = 'clk'
Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X2_Y4_N8; Fanout = 5; REG Node = 'count[3]'
Info: Total cell delay = 2.081 ns ( 62.16 % )
Info: Total interconnect delay = 1.267 ns ( 37.84 % )
Info: - Longest clock path from clock "clk" to source register is 3.348 ns
Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_E1; Fanout = 5; CLK Node = 'clk'
Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X2_Y4_N8; Fanout = 5; REG Node = 'count[3]'
Info: Total cell delay = 2.081 ns ( 62.16 % )
Info: Total interconnect delay = 1.267 ns ( 37.84 % )
Info: + Micro clock to output delay of source is 0.376 ns
Info: + Micro setup delay of destination is 0.333 ns
Info: tco from clock "clk" to destination pin "q" through register "q~reg0" is 6.854 ns
Info: + Longest clock path from clock "clk" to source register is 3.348 ns
Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_E1; Fanout = 5; CLK Node = 'clk'
Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X2_Y4_N4; Fanout = 1; REG Node = 'q~reg0'
Info: Total cell delay = 2.081 ns ( 62.16 % )
Info: Total interconnect delay = 1.267 ns ( 37.84 % )
Info: + Micro clock to output delay of source is 0.376 ns
Info: + Longest register to pin delay is 3.130 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y4_N4; Fanout = 1; REG Node = 'q~reg0'
Info: 2: + IC(0.808 ns) + CELL(2.322 ns) = 3.130 ns; Loc. = PIN_C1; Fanout = 0; PIN Node = 'q'
Info: Total cell delay = 2.322 ns ( 74.19 % )
Info: Total interconnect delay = 0.808 ns ( 25.81 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
Info: Allocated 98 megabytes of memory during processing
Info: Processing ended: Wed Apr 01 08:37:38 2009
Info: Elapsed time: 00:00:00
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -