div.fit.rpt

本人学士时候用的本人学士时候用的本人学士时候用的

+--------------------+-------+
; Name               ; Value ;
+--------------------+-------+
; Status Code        ; 0     ;
; Desired User Slack ; 0     ;
; Fit Attempts       ; 1     ;
+--------------------+-------+


+----------------------------------------------------------------------------------------+
; Advanced Data - Placement Preparation                                                  ;
+--------------------------------------------------------------------------------+-------+
; Name                                                                           ; Value ;
+--------------------------------------------------------------------------------+-------+
; Auto Fit Point 1 - Fit Attempt 1                                               ; ff    ;
; Mid Wire Use - Fit Attempt 1                                                   ; 0     ;
; Mid Slack - Fit Attempt 1                                                      ; -9753 ;
; Internal Atom Count - Fit Attempt 1                                            ; 5     ;
; LE/ALM Count - Fit Attempt 1                                                   ; 5     ;
; LAB Count - Fit Attempt 1                                                      ; 1     ;
; Outputs per Lab - Fit Attempt 1                                                ; 1.000 ;
; Inputs per LAB - Fit Attempt 1                                                 ; 0.000 ;
; Global Inputs per LAB - Fit Attempt 1                                          ; 1.000 ;
; LAB Constraint 'non-global clock / CE pair + async load' - Fit Attempt 1       ; 0:1   ;
; LAB Constraint 'ce + sync load' - Fit Attempt 1                                ; 0:1   ;
; LAB Constraint 'non-global controls' - Fit Attempt 1                           ; 0:1   ;
; LAB Constraint 'un-route combination' - Fit Attempt 1                          ; 0:1   ;
; LAB Constraint 'non-global with asyn_clear' - Fit Attempt 1                    ; 0:1   ;
; LAB Constraint 'un-route with async_clear' - Fit Attempt 1                     ; 0:1   ;
; LAB Constraint 'non-global async clear + sync clear' - Fit Attempt 1           ; 0:1   ;
; LAB Constraint 'global non-clock/non-asynch_clear' - Fit Attempt 1             ; 0:1   ;
; LAB Constraint 'ygr_cl_ngclk_gclkce_sload_aload_constraint' - Fit Attempt 1    ; 0:1   ;
; LAB Constraint 'global control signals' - Fit Attempt 1                        ; 1:1   ;
; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1                    ; 1:1   ;
; LAB Constraint 'aload_aclr pair with aload used' - Fit Attempt 1               ; 0:1   ;
; LAB Constraint 'aload_aclr pair' - Fit Attempt 1                               ; 1:1   ;
; LAB Constraint 'sload_sclear pair' - Fit Attempt 1                             ; 0:1   ;
; LAB Constraint 'invert_a constraint' - Fit Attempt 1                           ; 1:1   ;
; LAB Constraint 'has placement constraint' - Fit Attempt 1                      ; 0:1   ;
; LAB Constraint 'use of ADATA or SDATA by registers constraint' - Fit Attempt 1 ; 0:1   ;
; LEs in Chains - Fit Attempt 1                                                  ; 0     ;
; LEs in Long Chains - Fit Attempt 1                                             ; 0     ;
; LABs with Chains - Fit Attempt 1                                               ; 0     ;
; LABs with Multiple Chains - Fit Attempt 1                                      ; 0     ;
; Time - Fit Attempt 1                                                           ; 0     ;
+--------------------------------------------------------------------------------+-------+


+--------------------------------------------+
; Advanced Data - Placement                  ;
+------------------------------------+-------+
; Name                               ; Value ;
+------------------------------------+-------+
; Early Wire Use - Fit Attempt 1     ; 0     ;
; Early Slack - Fit Attempt 1        ; -8196 ;
; Auto Fit Point 2 - Fit Attempt 1   ; ff    ;
; Auto Fit Point 3 - Fit Attempt 1   ; ff    ;
; Auto Fit Point 4 - Fit Attempt 1   ; ff    ;
; Mid Wire Use - Fit Attempt 1       ; 0     ;
; Mid Slack - Fit Attempt 1          ; -7052 ;
; Late Wire Use - Fit Attempt 1      ; 0     ;
; Late Slack - Fit Attempt 1         ; -7052 ;
; Peak Regional Wire - Fit Attempt 1 ; 0.000 ;
; Auto Fit Point 5 - Fit Attempt 1   ; ff    ;
; Time - Fit Attempt 1               ; 0     ;
+------------------------------------+-------+


+---------------------------------------------+
; Advanced Data - Routing                     ;
+-------------------------------------+-------+
; Name                                ; Value ;
+-------------------------------------+-------+
; Early Wire Use - Fit Attempt 1      ; 0     ;
; Peak Regional Wire - Fit Attempt 1  ; 0     ;
; Early Slack - Fit Attempt 1         ; -6319 ;
; Mid Slack - Fit Attempt 1           ; -6319 ;
; Late Slack - Fit Attempt 1          ; -6319 ;
; Late Wire Use - Fit Attempt 1       ; 0     ;
; Time - Fit Attempt 1                ; 0     ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.016 ;
+-------------------------------------+-------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Wed Apr 01 08:37:32 2009
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off div -c div
Info: Selected device EPM240F100C5 for design "div"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EPM240F100I5 is compatible
    Info: Device EPM570F100C5 is compatible
    Info: Device EPM570F100I5 is compatible
Warning: No exact pin location assignment(s) for 2 pins of 2 total pins
    Info: Pin q not assigned to an exact location on the device
    Info: Pin clk not assigned to an exact location on the device
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1000 MHz
    Info: Assuming a global tsu requirement of 2.0 ns
    Info: Assuming a global tco requirement of 1.0 ns
    Info: Assuming a global tpd requirement of 1.0 ns
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "clk" to use Global clock in PIN E1
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished register packing: elapsed time is 00:00:00
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 1 (unused VREF, 3.30 VCCIO, 0 input, 1 output, 0 bidirectional)
        Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  37 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  42 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to pin delay of 2.913 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X2_Y4; Fanout = 1; REG Node = 'q~reg0'
    Info: 2: + IC(0.591 ns) + CELL(2.322 ns) = 2.913 ns; Loc. = PIN_C1; Fanout = 0; PIN Node = 'q'
    Info: Total cell delay = 2.322 ns ( 79.71 % )
    Info: Total interconnect delay = 0.591 ns ( 20.29 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%
    Info: The peak interconnect region extends from location X0_Y0 to location X8_Y5
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Quartus II Fitter was successful. 0 errors, 2 warnings
    Info: Allocated 146 megabytes of memory during processing
    Info: Processing ended: Wed Apr 01 08:37:33 2009
    Info: Elapsed time: 00:00:01


+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in D:/VHDL/div/div.fit.smsg.