div.vhd

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity div is
generic(duty:integer:=5);
port(clk: in std_logic;
	   q: out std_logic
	);
	
end div;
	
architecture div10 of div is
constant period : integer:=10;
signal count : integer range 0 to period-1;
begin
process(clk)	--jincheng
begin
 if rising_edge(clk) then
    q<='1';
    if count < duty then 
		q<='0';
		count<=count+1;
	elsif count<period-1 then
		count<=count+1;
	else 
	count <= 0;
	end if;
end if;
end process	;
end div10;