📄 stm32f10x_tim.txt
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;;;1087
;;;1088 TIMx->CCMR1 = (u16)tmpccmr1;
00050c 8301 STRH r1,[r0,#0x18]
;;;1089 }
00050e 4770 BX lr
;;;1090
ENDP
TIM_OC3PreloadConfig PROC
;;;1109
;;;1110 tmpccmr2 = TIMx->CCMR2;
000510 8b82 LDRH r2,[r0,#0x1c]
;;;1111
;;;1112 /* Reset the OCPE Bit */
;;;1113 tmpccmr2 &= CCMR_OC13PE_Mask;
000512 f6477377 MOV r3,#0x7f77
000516 401a ANDS r2,r2,r3
;;;1114
;;;1115 /* Enable or Disable the Output Compare Preload feature */
;;;1116 tmpccmr2 |= TIM_OCPreload;
000518 4311 ORRS r1,r1,r2
;;;1117
;;;1118 TIMx->CCMR2 = (u16)tmpccmr2;
00051a 8381 STRH r1,[r0,#0x1c]
;;;1119 }
00051c 4770 BX lr
;;;1120
ENDP
TIM_OC4PreloadConfig PROC
;;;1139
;;;1140 tmpccmr2 = TIMx->CCMR2;
00051e 8b82 LDRH r2,[r0,#0x1c]
;;;1141
;;;1142 /* Reset the OCPE Bit */
;;;1143 tmpccmr2 &= CCMR_OC24PE_Mask;
000520 f247737f MOV r3,#0x777f
000524 401a ANDS r2,r2,r3
;;;1144
;;;1145 /* Enable or Disable the Output Compare Preload feature */
;;;1146 tmpccmr2 |= (u16)(TIM_OCPreload << 8);
000526 ea422101 ORR r1,r2,r1,LSL #8
;;;1147
;;;1148 TIMx->CCMR2 = (u16)tmpccmr2;
00052a 8381 STRH r1,[r0,#0x1c]
;;;1149 }
00052c 4770 BX lr
;;;1150
ENDP
TIM_OC1FastConfig PROC
;;;1168
;;;1169 tmpccmr1 = TIMx->CCMR1;
00052e 8b02 LDRH r2,[r0,#0x18]
;;;1170
;;;1171 /* Reset the OCFE Bit */
;;;1172 tmpccmr1 &= CCMR_OC13FE_Mask;
000530 f647737b MOV r3,#0x7f7b
000534 401a ANDS r2,r2,r3
;;;1173
;;;1174 /* Enable or Disable the Output Compare Fast Bit */
;;;1175 tmpccmr1 |= TIM_OCFast;
000536 4311 ORRS r1,r1,r2
;;;1176
;;;1177 TIMx->CCMR1 = (u16)tmpccmr1;
000538 8301 STRH r1,[r0,#0x18]
;;;1178 }
00053a 4770 BX lr
;;;1179
ENDP
TIM_OC2FastConfig PROC
;;;1197
;;;1198 tmpccmr1 = TIMx->CCMR1;
00053c 8b02 LDRH r2,[r0,#0x18]
;;;1199
;;;1200 /* Reset the OCFE Bit */
;;;1201 tmpccmr1 &= CCMR_OC24FE_Mask;
00053e f647337f MOV r3,#0x7b7f
000542 401a ANDS r2,r2,r3
;;;1202
;;;1203 /* Enable or Disable the Output Compare Fast Bit */
;;;1204 tmpccmr1 |= (u16)(TIM_OCFast << 8);
000544 ea422101 ORR r1,r2,r1,LSL #8
;;;1205
;;;1206 TIMx->CCMR1 = (u16)tmpccmr1;
000548 8301 STRH r1,[r0,#0x18]
;;;1207 }
00054a 4770 BX lr
;;;1208
ENDP
TIM_OC3FastConfig PROC
;;;1226
;;;1227 tmpccmr2 = TIMx->CCMR2;
00054c 8b82 LDRH r2,[r0,#0x1c]
;;;1228
;;;1229 /* Reset the OCFE Bit */
;;;1230 tmpccmr2 &= CCMR_OC13FE_Mask;
00054e f647737b MOV r3,#0x7f7b
000552 401a ANDS r2,r2,r3
;;;1231
;;;1232 /* Enable or Disable the Output Compare Fast Bit */
;;;1233 tmpccmr2 |= TIM_OCFast;
000554 4311 ORRS r1,r1,r2
;;;1234
;;;1235 TIMx->CCMR2 = (u16)tmpccmr2;
000556 8381 STRH r1,[r0,#0x1c]
;;;1236 }
000558 4770 BX lr
;;;1237
ENDP
TIM_OC4FastConfig PROC
;;;1255
;;;1256 tmpccmr2 = TIMx->CCMR2;
00055a 8b82 LDRH r2,[r0,#0x1c]
;;;1257
;;;1258 /* Reset the OCFE Bit */
;;;1259 tmpccmr2 &= CCMR_OC24FE_Mask;
00055c f647337f MOV r3,#0x7b7f
000560 401a ANDS r2,r2,r3
;;;1260
;;;1261 /* Enable or Disable the Output Compare Fast Bit */
;;;1262 tmpccmr2 |= (u16)(TIM_OCFast << 8);
000562 ea422101 ORR r1,r2,r1,LSL #8
;;;1263
;;;1264 TIMx->CCMR2 = (u16)tmpccmr2;
000566 8381 STRH r1,[r0,#0x1c]
;;;1265 }
000568 4770 BX lr
;;;1266
ENDP
TIM_ClearOC1Ref PROC
;;;1284
;;;1285 tmpccmr1 = TIMx->CCMR1;
00056a 8b02 LDRH r2,[r0,#0x18]
;;;1286
;;;1287 /* Reset the OCFE Bit */
;;;1288 tmpccmr1 &= CCMR_OC13CE_Mask;
00056c f64f737f MOV r3,#0xff7f
000570 401a ANDS r2,r2,r3
;;;1289
;;;1290 /* Enable or Disable the Output Compare Clear Bit */
;;;1291 tmpccmr1 |= (u16)(TIM_OCClear);
000572 4311 ORRS r1,r1,r2
;;;1292
;;;1293 TIMx->CCMR1 = (u16)tmpccmr1;
000574 8301 STRH r1,[r0,#0x18]
;;;1294 }
000576 4770 BX lr
;;;1295
ENDP
TIM_ClearOC2Ref PROC
;;;1313
;;;1314 tmpccmr1 = TIMx->CCMR1;
000578 8b02 LDRH r2,[r0,#0x18]
;;;1315
;;;1316 /* Reset the OCFE Bit */
;;;1317 tmpccmr1 &= CCMR_OC24CE_Mask;
00057a f3c2020e UBFX r2,r2,#0,#15
;;;1318
;;;1319 /* Enable or Disable the Output Compare Clear Bit */
;;;1320 tmpccmr1 |= (u16)(TIM_OCClear << 8);
00057e ea422101 ORR r1,r2,r1,LSL #8
;;;1321
;;;1322 TIMx->CCMR1 = (u16)tmpccmr1;
000582 8301 STRH r1,[r0,#0x18]
;;;1323 }
000584 4770 BX lr
;;;1324
ENDP
TIM_ClearOC3Ref PROC
;;;1342
;;;1343 tmpccmr2 = TIMx->CCMR2;
000586 8b82 LDRH r2,[r0,#0x1c]
;;;1344
;;;1345 /* Reset the OCFE Bit */
;;;1346 tmpccmr2 &= CCMR_OC13CE_Mask;
000588 f64f737f MOV r3,#0xff7f
00058c 401a ANDS r2,r2,r3
;;;1347
;;;1348 /* Enable or Disable the Output Compare Clear Bit */
;;;1349 tmpccmr2 |= (u16)(TIM_OCClear);
00058e 4311 ORRS r1,r1,r2
;;;1350
;;;1351 TIMx->CCMR2 = (u16)tmpccmr2;
000590 8381 STRH r1,[r0,#0x1c]
;;;1352 }
000592 4770 BX lr
;;;1353
ENDP
TIM_ClearOC4Ref PROC
;;;1371
;;;1372 tmpccmr2 = TIMx->CCMR2;
000594 8b82 LDRH r2,[r0,#0x1c]
;;;1373
;;;1374 /* Reset the OCFE Bit */
;;;1375 tmpccmr2 &= CCMR_OC24CE_Mask;
000596 f3c2020e UBFX r2,r2,#0,#15
;;;1376
;;;1377 /* Enable or Disable the Output Compare Clear Bit */
;;;1378 tmpccmr2 |= (u16)(TIM_OCClear << 8);
00059a ea422101 ORR r1,r2,r1,LSL #8
;;;1379
;;;1380 TIMx->CCMR2 = (u16)tmpccmr2;
00059e 8381 STRH r1,[r0,#0x1c]
;;;1381 }
0005a0 4770 BX lr
;;;1382
ENDP
TIM_UpdateDisableConfig PROC
;;;1398
;;;1399 tmpcr1 = TIMx->CR1;
0005a2 8802 LDRH r2,[r0,#0]
;;;1400
;;;1401 if (Newstate != DISABLE)
0005a4 b111 CBZ r1,|L1.1452|
;;;1402 {
;;;1403 /* Set the Update Disable Bit */
;;;1404 tmpcr1 |= CR1_UDIS_Set;
0005a6 f0420102 ORR r1,r2,#2
0005aa e002 B |L1.1458|
|L1.1452|
;;;1405 }
;;;1406 else
;;;1407 {
;;;1408 /* Reset the Update Disable Bit */
;;;1409 tmpcr1 &= CR1_UDIS_Reset;
0005ac f24031fd MOV r1,#0x3fd
0005b0 4011 ANDS r1,r1,r2
|L1.1458|
;;;1410 }
;;;1411
;;;1412 TIMx->CR1 = (u16)tmpcr1;
0005b2 8001 STRH r1,[r0,#0]
;;;1413 }
0005b4 4770 BX lr
;;;1414
ENDP
TIM_EncoderInterfaceConfig PROC
;;;1439 u16 TIM_IC1Polarity, u16 TIM_IC2Polarity)
;;;1440 {
0005b6 b470 PUSH {r4-r6}
;;;1441 u32 tmpsmcr = 0;
;;;1442 u32 tmpccmr1 = 0;
;;;1443 u32 tmpccer = 0;
;;;1444
;;;1445 /* Check the parameters */
;;;1446 assert(IS_TIM_ENCODER_MODE(TIM_EncoderMode));
;;;1447 assert(IS_TIM_IC_POLARITY(TIM_IC1Polarity));
;;;1448 assert(IS_TIM_IC_POLARITY(TIM_IC2Polarity));
;;;1449
;;;1450 tmpsmcr = TIMx->SMCR;
0005b8 8905 LDRH r5,[r0,#8]
;;;1451 tmpccmr1 = TIMx->CCMR1;
0005ba 8b04 LDRH r4,[r0,#0x18]
;;;1452 tmpccer = TIMx->CCER;
0005bc f8b0c020 LDRH r12,[r0,#0x20]
;;;1453
;;;1454 /* Set the encoder Mode */
;;;1455 tmpsmcr &= SMCR_SMS_Mask;
0005c0 f64f76f0 MOV r6,#0xfff0
0005c4 4035 ANDS r5,r5,r6
;;;1456 tmpsmcr |= TIM_EncoderMode;
0005c6 4329 ORRS r1,r1,r5
;;;1457
;;;1458 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
;;;1459 tmpccmr1 &= CCMR_CC13S_Mask & CCMR_CC24S_Mask;
0005c8 f647457c MOV r5,#0x7c7c
0005cc 402c ANDS r4,r4,r5
;;;1460 tmpccmr1 |= CCMR_TI13Direct_Set | CCMR_TI24Direct_Set;
0005ce f2401501 MOV r5,#0x101
0005d2 432c ORRS r4,r4,r5
;;;1461
;;;1462 /* Set the TI1 and the TI2 Polarities */
;;;1463 tmpccer &= CCER_CC1P_Mask & CCER_CC2P_Mask;
0005d4 f64f75dd MOV r5,#0xffdd
0005d8 ea0c0c05 AND r12,r12,r5
;;;1464 tmpccer |= (TIM_IC1Polarity | (u16)((u16)TIM_IC2Polarity << 4));
0005dc ea421203 ORR r2,r2,r3,LSL #4
0005e0 ea42020c ORR r2,r2,r12
;;;1465
;;;1466 TIMx->SMCR = (u16)tmpsmcr;
0005e4 8101 STRH r1,[r0,#8]
;;;1467
;;;1468 TIMx->CCMR1 = (u16)tmpccmr1;
0005e6 8304 STRH r4,[r0,#0x18]
;;;1469
;;;1470 TIMx->CCER = (u16)tmpccer;
0005e8 8402 STRH r2,[r0,#0x20]
;;;1471 }
0005ea bc70 POP {r4-r6}
0005ec 4770 BX lr
;;;1472
ENDP
TIM_GenerateEvent PROC
;;;1493 /* Set the event sources */
;;;1494 TIMx->EGR |= TIM_EventSource;
0005ee 8a82 LDRH r2,[r0,#0x14]
0005f0 4311 ORRS r1,r1,r2
0005f2 8281 STRH r1,[r0,#0x14]
;;;1495 }
0005f4 4770 BX lr
;;;1496
ENDP
TIM_OC1PolarityConfig PROC
;;;1514
;;;1515 tmpccer = TIMx->CCER;
0005f6 8c02 LDRH r2,[r0,#0x20]
;;;1516
;;;1517 /* Set or Reset the CC1P Bit */
;;;1518 tmpccer &= CCER_CC1P_Mask;
0005f8 f64f73fd MOV r3,#0xfffd
0005fc 401a ANDS r2,r2,r3
;;;1519 tmpccer |= TIM_OCPolarity;
0005fe 4311 ORRS r1,r1,r2
;;;1520
;;;1521 TIMx->CCER = (u16)tmpccer;
000600 8401 STRH r1,[r0,#0x20]
;;;1522 }
000602 4770 BX lr
;;;1523
ENDP
TIM_OC2PolarityConfig PROC
;;;1541
;;;1542 tmpccer = TIMx->CCER;
000604 8c02 LDRH r2,[r0,#0x20]
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