📄 stm32f10x_adc.txt
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;;;460 }
;;;461 /* Return the SWSTRT bit status */
;;;462 return bitstatus;
;;;463 }
000136 4770 BX lr
;;;464
ENDP
ADC_DiscModeChannelCountConfig PROC
;;;483 /* Get the old register value */
;;;484 tmpreg1 = ADCx->CR1;
000138 6842 LDR r2,[r0,#4]
;;;485 /* Clear the old discontinuous mode channel count */
;;;486 tmpreg1 &= CR1_DISCNUM_Reset;
00013a f4224260 BIC r2,r2,#0xe000
;;;487 /* Set the discontinuous mode channel count */
;;;488 tmpreg2 = Number - 1;
00013e 1e49 SUBS r1,r1,#1
000140 b2c9 UXTB r1,r1
;;;489 tmpreg1 |= ((u32)tmpreg2 << 13);
000142 ea423141 ORR r1,r2,r1,LSL #13
;;;490 /* Store the new register value */
;;;491 ADCx->CR1 = tmpreg1;
000146 6041 STR r1,[r0,#4]
;;;492 }
000148 4770 BX lr
;;;493
ENDP
ADC_DiscModeCmd PROC
;;;509
;;;510 if (NewState != DISABLE)
00014a b121 CBZ r1,|L1.342|
;;;511 {
;;;512 /* Enable the selected ADC regular discontinuous mode */
;;;513 ADCx->CR1 |= CR1_DISCEN_Set;
00014c 6841 LDR r1,[r0,#4]
00014e f4416100 ORR r1,r1,#0x800
000152 6041 STR r1,[r0,#4]
;;;514 }
;;;515 else
;;;516 {
;;;517 /* Disable the selected ADC regular discontinuous mode */
;;;518 ADCx->CR1 &= CR1_DISCEN_Reset;
;;;519 }
;;;520 }
000154 4770 BX lr
|L1.342|
000156 6841 LDR r1,[r0,#4] ;518
000158 f4216100 BIC r1,r1,#0x800 ;518
00015c 6041 STR r1,[r0,#4] ;518
00015e 4770 BX lr
;;;521
ENDP
ADC_RegularChannelConfig PROC
;;;563 void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel, u8 Rank, u8 ADC_SampleTime)
;;;564 {
000160 b430 PUSH {r4,r5}
;;;565 u32 tmpreg1 = 0, tmpreg2 = 0;
;;;566
;;;567 /* Check the parameters */
;;;568 assert(IS_ADC_CHANNEL(ADC_Channel));
;;;569 assert(IS_ADC_REGULAR_RANK(Rank));
;;;570 assert(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
;;;571
;;;572 /* if ADC_Channel_10 ... ADC_Channel_17 is selected */
;;;573 if (ADC_Channel > ADC_Channel_9)
000162 2507 MOVS r5,#7
000164 2909 CMP r1,#9
000166 d90c BLS |L1.386|
;;;574 {
;;;575 /* Get the old register value */
;;;576 tmpreg1 = ADCx->SMPR1;
000168 68c4 LDR r4,[r0,#0xc]
;;;577 /* Calculate the mask to clear */
;;;578 tmpreg2 = (u32)SMPR1_SMP_Set << (3 * (ADC_Channel - 10));
00016a f1a10c0a SUB r12,r1,#0xa
00016e eb0c0c4c ADD r12,r12,r12,LSL #1
000172 fa05f50c LSL r5,r5,r12
;;;579 /* Clear the old discontinuous mode channel count */
;;;580 tmpreg1 &= ~tmpreg2;
000176 43ac BICS r4,r4,r5
;;;581 /* Calculate the mask to set */
;;;582 tmpreg2 = (u32)ADC_SampleTime << (3 * (ADC_Channel - 10));
000178 fa03f30c LSL r3,r3,r12
;;;583 /* Set the discontinuous mode channel count */
;;;584 tmpreg1 |= tmpreg2;
00017c 4323 ORRS r3,r3,r4
;;;585 /* Store the new register value */
;;;586 ADCx->SMPR1 = tmpreg1;
00017e 60c3 STR r3,[r0,#0xc]
000180 e009 B |L1.406|
|L1.386|
;;;587 }
;;;588 else /* ADC_Channel include in ADC_Channel_[0..9] */
;;;589 {
;;;590 /* Get the old register value */
;;;591 tmpreg1 = ADCx->SMPR2;
000182 6904 LDR r4,[r0,#0x10]
;;;592 /* Calculate the mask to clear */
;;;593 tmpreg2 = (u32)SMPR2_SMP_Set << (3 * ADC_Channel);
000184 eb010c41 ADD r12,r1,r1,LSL #1
000188 fa05f50c LSL r5,r5,r12
;;;594 /* Clear the old discontinuous mode channel count */
;;;595 tmpreg1 &= ~tmpreg2;
00018c 43ac BICS r4,r4,r5
;;;596 /* Calculate the mask to set */
;;;597 tmpreg2 = (u32)ADC_SampleTime << (3 * ADC_Channel);
00018e fa03f30c LSL r3,r3,r12
;;;598 /* Set the discontinuous mode channel count */
;;;599 tmpreg1 |= tmpreg2;
000192 4323 ORRS r3,r3,r4
;;;600 /* Store the new register value */
;;;601 ADCx->SMPR2 = tmpreg1;
000194 6103 STR r3,[r0,#0x10]
|L1.406|
;;;602 }
;;;603 /* For Rank 1 to 6 */
;;;604 if (Rank < 7)
000196 f04f0c1f MOV r12,#0x1f
00019a 2a07 CMP r2,#7
00019c d20c BCS |L1.440|
;;;605 {
;;;606 /* Get the old register value */
;;;607 tmpreg1 = ADCx->SQR3;
00019e 6b43 LDR r3,[r0,#0x34]
;;;608 /* Calculate the mask to clear */
;;;609 tmpreg2 = (u32)SQR3_SQ_Set << (5 * (Rank - 1));
0001a0 1e52 SUBS r2,r2,#1
0001a2 eb020282 ADD r2,r2,r2,LSL #2
0001a6 fa0cfc02 LSL r12,r12,r2
;;;610 /* Clear the old SQx bits for the selected rank */
;;;611 tmpreg1 &= ~tmpreg2;
0001aa ea23030c BIC r3,r3,r12
;;;612 /* Calculate the mask to set */
;;;613 tmpreg2 = (u32)ADC_Channel << (5 * (Rank - 1));
0001ae 4091 LSLS r1,r1,r2
;;;614 /* Set the SQx bits for the selected rank */
;;;615 tmpreg1 |= tmpreg2;
0001b0 4319 ORRS r1,r1,r3
;;;616 /* Store the new register value */
;;;617 ADCx->SQR3 = tmpreg1;
0001b2 6341 STR r1,[r0,#0x34]
;;;618 }
;;;619 /* For Rank 7 to 12 */
;;;620 else if (Rank < 13)
;;;621 {
;;;622 /* Get the old register value */
;;;623 tmpreg1 = ADCx->SQR2;
;;;624 /* Calculate the mask to clear */
;;;625 tmpreg2 = (u32)SQR2_SQ_Set << (5 * (Rank - 7));
;;;626 /* Clear the old SQx bits for the selected rank */
;;;627 tmpreg1 &= ~tmpreg2;
;;;628 /* Calculate the mask to set */
;;;629 tmpreg2 = (u32)ADC_Channel << (5 * (Rank - 7));
;;;630 /* Set the SQx bits for the selected rank */
;;;631 tmpreg1 |= tmpreg2;
;;;632 /* Store the new register value */
;;;633 ADCx->SQR2 = tmpreg1;
;;;634 }
;;;635 /* For Rank 13 to 16 */
;;;636 else
;;;637 {
;;;638 /* Get the old register value */
;;;639 tmpreg1 = ADCx->SQR1;
;;;640 /* Calculate the mask to clear */
;;;641 tmpreg2 = (u32)SQR1_SQ_Set << (5 * (Rank - 13));
;;;642 /* Clear the old SQx bits for the selected rank */
;;;643 tmpreg1 &= ~tmpreg2;
;;;644 /* Calculate the mask to set */
;;;645 tmpreg2 = (u32)ADC_Channel << (5 * (Rank - 13));
;;;646 /* Set the SQx bits for the selected rank */
;;;647 tmpreg1 |= tmpreg2;
;;;648 /* Store the new register value */
;;;649 ADCx->SQR1 = tmpreg1;
;;;650 }
;;;651 }
0001b4 bc30 POP {r4,r5}
0001b6 4770 BX lr
|L1.440|
0001b8 2a0d CMP r2,#0xd ;620
0001ba d20c BCS |L1.470|
0001bc 6b03 LDR r3,[r0,#0x30] ;623
0001be 1fd2 SUBS r2,r2,#7 ;625
0001c0 eb020282 ADD r2,r2,r2,LSL #2 ;625
0001c4 fa0cfc02 LSL r12,r12,r2 ;625
0001c8 ea23030c BIC r3,r3,r12 ;627
0001cc 4091 LSLS r1,r1,r2 ;629
0001ce 4319 ORRS r1,r1,r3 ;631
0001d0 6301 STR r1,[r0,#0x30] ;633
0001d2 bc30 POP {r4,r5}
0001d4 4770 BX lr
|L1.470|
0001d6 6ac3 LDR r3,[r0,#0x2c] ;639
0001d8 3a0d SUBS r2,r2,#0xd ;641
0001da eb020282 ADD r2,r2,r2,LSL #2 ;641
0001de fa0cfc02 LSL r12,r12,r2 ;641
0001e2 ea23030c BIC r3,r3,r12 ;643
0001e6 4091 LSLS r1,r1,r2 ;645
0001e8 4319 ORRS r1,r1,r3 ;647
0001ea 62c1 STR r1,[r0,#0x2c] ;649
0001ec bc30 POP {r4,r5}
0001ee 4770 BX lr
;;;652
ENDP
ADC_ExternalTrigConvCmd PROC
;;;667
;;;668 if (NewState != DISABLE)
0001f0 b121 CBZ r1,|L1.508|
;;;669 {
;;;670 /* Enable the selected ADC conversion on external event */
;;;671 ADCx->CR2 |= CR2_EXTTRIG_Set;
0001f2 6881 LDR r1,[r0,#8]
0001f4 f4411180 ORR r1,r1,#0x100000
0001f8 6081 STR r1,[r0,#8]
;;;672 }
;;;673 else
;;;674 {
;;;675 /* Disable the selected ADC conversion on external event */
;;;676 ADCx->CR2 &= CR2_EXTTRIG_Reset;
;;;677 }
;;;678 }
0001fa 4770 BX lr
|L1.508|
0001fc 6881 LDR r1,[r0,#8] ;676
0001fe f4211180 BIC r1,r1,#0x100000 ;676
000202 6081 STR r1,[r0,#8] ;676
000204 4770 BX lr
;;;679
ENDP
ADC_GetConversionValue PROC
;;;689 /* Return the selected ADC conversion value */
;;;690 return (u16) ADCx->DR;
000206 6cc0 LDR r0,[r0,#0x4c]
000208 b280 UXTH r0,r0
;;;691 }
00020a 4770 BX lr
;;;692
ENDP
ADC_GetDualModeConversionValue PROC
;;;701 /* Return the dual mode conversion value */
;;;702 return ADC1->DR;
00020c 485e LDR r0,|L1.904|
00020e 6800 LDR r0,[r0,#0]
;;;703 }
000210 4770 BX lr
;;;704
ENDP
ADC_AutoInjectedConvCmd PROC
;;;720
;;;721 if (NewState != DISABLE)
000212 b121 CBZ r1,|L1.542|
;;;722 {
;;;723 /* Enable the selected ADC automatic injected group conversion */
;;;724 ADCx->CR1 |= CR1_JAUTO_Set;
000214 6841 LDR r1,[r0,#4]
000216 f4416180 ORR r1,r1,#0x400
00021a 6041 STR r1,[r0,#4]
;;;725 }
;;;726 else
;;;727 {
;;;728 /* Disable the selected ADC automatic injected group conversion */
;;;729 ADCx->CR1 &= CR1_JAUTO_Reset;
;;;730 }
;;;731 }
00021c 4770 BX lr
|L1.542|
00021e 6841 LDR r1,[r0,#4] ;729
000220 f4216180 BIC r1,r1,#0x400 ;729
000224 6041 STR r1,[r0,#4] ;729
000226 4770 BX lr
;;;732
ENDP
ADC_InjectedDiscModeCmd PROC
;;;748
;;;749 if (NewState != DISABLE)
000228 b121 CBZ r1,|L1.564|
;;;750 {
;;;751 /* Enable the selected ADC injected discontinuous mode */
;;;752 ADCx->CR1 |= CR1_JDISCEN_Set;
00022a 6841 LDR r1,[r0,#4]
00022c f4415180 ORR r1,r1,#0x1000
000230 6041 STR r1,[r0,#4]
;;;753 }
;;;754 else
;;;755 {
;;;756 /* Disable the selected ADC injected discontinuous mode */
;;;757 ADCx->CR1 &= CR1_JDISCEN_Reset;
;;;758 }
;;;759 }
000232 4770 BX lr
|L1.564|
000234 6841 LDR r1,[r0,#4] ;757
000236 f4215180 BIC r1,r1,#0x1000 ;757
00023a 6041 STR r1,[r0,#4] ;757
00023c 4770 BX lr
;;;760
ENDP
ADC_ExternalTrigInjectedConvConfig PROC
;;;794 /* Get the old register value */
;;;795 tmpreg = ADCx->CR2;
00023e 6882 LDR r2,[r0,#8]
;;;796 /* Clear the old external event selection for injected group */
;;;797 tmpreg &= CR2_JEXTSEL_Reset;
000240 f42242e0 BIC r2,r2,#0x7000
;;;798 /* Set the external event selection for injected group */
;;;799 tmpreg |= ADC_ExternalTrigInjecConv;
000244 4311 ORRS r1,r1,r2
;;;800 /* Store the new register value */
;;;801 ADCx->CR2 = tmpreg;
000246 6081 STR r1,[r0,#8]
;;;802 }
000248 4770 BX lr
;;;803
ENDP
ADC_ExternalTrigInjectedConvCmd PROC
;;;819
;;;820 if (NewState != DISABLE)
00024a b121 CBZ r1,|L1.598|
;;;821 {
;;;822 /* Enable the selected ADC external event selection for injected group */
;;;823 ADCx->CR2 |= CR2_JEXTTRIG_Set;
00024c 6881 LDR r1,[r0,#8]
00024e f4414100 ORR r1,r1,#0x8000
000252 6081 STR r1,[r0,#8]
;;;824 }
;;;825 else
;;;826 {
;;;827 /* Disable the selected ADC external event selection for injected group */
;;;828 ADCx->CR2 &= CR2_JEXTTRIG_Reset;
;;;829 }
;;;830 }
000254 4770 BX lr
|L1.598|
000256 6881 LDR r1,[r0,#8] ;828
000258 f4214100 BIC r1,r1,#0x8000 ;828
00025c 6081 STR r1,[r0,#8] ;828
00025e 4770 BX lr
;;;831
ENDP
ADC_SoftwareStartInjectedConvCmd PROC
;;;847
;;;848 if (NewState != DISABLE)
000260 b121 CBZ r1,|L1.620|
;;;849 {
;;;850 /* Enable the selected ADC external event selection for injected group */
;;;851 /* Starts the selected ADC injected conversion */
;;;852 ADCx->CR2 |= CR2_JEXTTRIG_JSWSTRT_Set;
000262 6881 LDR r1,[r0,#8]
000264 f4411102 ORR r1,r1,#0x208000
000268 6081 STR r1,[r0,#8]
;;;853 }
;;;854 else
;;;855 {
;;;856 /* Stops the selected ADC injected conversion */
;;;857 /* Disable the selected ADC external event selection for injected group */
;;;858 ADCx->CR2 &= CR2_JEXTTRIG_JSWSTRT_Reset;
;;;859 }
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