📄 stm32f10x_adc.txt
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; generated by ARM/Thumb C/C++ Compiler with , RVCT3.1 [Build 942] for uVision
; commandline ArmCC [--debug -c --asm --interleave -o.\rvmdk\stm32f10x_adc.o --depend=.\rvmdk\stm32f10x_adc.d --device=DARMSTM --apcs=interwork -O1 -Otime -I. -I..\BSP -I..\..\..\..\..\uCOS-II\Ports\arm-cortex-m3\Generic\RealView -I..\..\..\..\..\uCOS-II\Source -I..\..\..\..\..\CPU\ST\STM32\inc -I..\..\..\..\..\uC-CPU -I..\..\..\..\..\uC-CPU\Arm-Cortex-M3\RealView -I..\..\..\..\..\uC-LIB -I..\..\..\..\..\uC-Probe\Target\Plugins\uCOS-II -I..\..\..\..\..\uC-Probe\Target\Communication\Generic\Source -I..\..\..\..\..\uC-Probe\Target\Communication\Generic\RS-232\Ports\ST\STM32 -I..\..\..\..\..\uC-Probe\Target\Communication\Generic\RS-232\Source -IC:\Keil\ARM\INC\ST\STM32F10x ..\..\..\..\..\CPU\ST\STM32\src\stm32f10x_adc.c]
THUMB
AREA ||.text||, CODE, READONLY, ALIGN=2
ADC_DeInit PROC
;;;127 void ADC_DeInit(ADC_TypeDef* ADCx)
;;;128 {
000000 b510 PUSH {r4,lr}
;;;129 switch (*(u32*)&ADCx)
000002 f1a04080 SUB r0,r0,#0x40000000
000006 f5b03092 SUBS r0,r0,#0x12400
00000a d00d BEQ |L1.40|
00000c f5b06f80 CMP r0,#0x400
000010 d115 BNE |L1.62|
;;;130 {
;;;131 case ADC1_BASE:
;;;132 /* Enable ADC1 reset state */
;;;133 RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE);
;;;134 /* Release ADC1 from reset state */
;;;135 RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE);
;;;136 break;
;;;137
;;;138 case ADC2_BASE:
;;;139 /* Enable ADC2 reset state */
;;;140 RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, ENABLE);
000012 2101 MOVS r1,#1
000014 0288 LSLS r0,r1,#10
000016 f7fffffe BL RCC_APB2PeriphResetCmd
;;;141 /* Release ADC2 from reset state */
;;;142 RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, DISABLE);
00001a e8bd4010 POP {r4,lr}
00001e 2100 MOVS r1,#0
000020 f44f6080 MOV r0,#0x400
000024 f7ffbffe B.W RCC_APB2PeriphResetCmd
|L1.40|
000028 2101 MOVS r1,#1 ;133
00002a 0248 LSLS r0,r1,#9 ;133
00002c f7fffffe BL RCC_APB2PeriphResetCmd
000030 e8bd4010 POP {r4,lr} ;135
000034 2100 MOVS r1,#0 ;135
000036 f44f7000 MOV r0,#0x200 ;135
00003a f7ffbffe B.W RCC_APB2PeriphResetCmd
|L1.62|
;;;143 break;
;;;144
;;;145 default:
;;;146 break;
;;;147 }
;;;148 }
00003e bd10 POP {r4,pc}
;;;149
ENDP
ADC_Init PROC
;;;175 /* Get the ADCx CR1 value */
;;;176 tmpreg1 = ADCx->CR1;
000040 6842 LDR r2,[r0,#4]
;;;177 /* Clear DUALMODE and SCAN bits */
;;;178 tmpreg1 &= CR1_CLEAR_Mask;
000042 f4227280 BIC r2,r2,#0x100
000046 f4222270 BIC r2,r2,#0xf0000
;;;179 /* Configure ADCx: Dual mode and scan conversion mode */
;;;180 /* Set DUALMODE bits according to ADC_Mode value */
;;;181 /* Set SCAN bit according to ADC_ScanConvMode value */
;;;182 tmpreg1 |= (u32)(ADC_InitStruct->ADC_Mode | ((u32)ADC_InitStruct->ADC_ScanConvMode << 8));
00004a f891c004 LDRB r12,[r1,#4]
00004e 680b LDR r3,[r1,#0]
000050 ea42220c ORR r2,r2,r12,LSL #8
000054 431a ORRS r2,r2,r3
;;;183 /* Write to ADCx CR1 */
;;;184 ADCx->CR1 = tmpreg1;
000056 6042 STR r2,[r0,#4]
;;;185
;;;186 /*---------------------------- ADCx CR2 Configuration -----------------*/
;;;187 /* Get the ADCx CR2 value */
;;;188 tmpreg1 = ADCx->CR2;
000058 6882 LDR r2,[r0,#8]
;;;189 /* Clear CONT, ALIGN and EXTTRIG bits */
;;;190 tmpreg1 &= CR2_CLEAR_Mask;
00005a 4bca LDR r3,|L1.900|
00005c 401a ANDS r2,r2,r3
;;;191 /* Configure ADCx: external trigger event and continuous conversion mode */
;;;192 /* Set ALIGN bit according to ADC_DataAlign value */
;;;193 /* Set EXTTRIG bits according to ADC_ExternalTrigConv value */
;;;194 /* Set CONT bit according to ADC_ContinuousConvMode value */
;;;195 tmpreg1 |= (u32)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv |
00005e f8d1c008 LDR r12,[r1,#8]
000062 68cb LDR r3,[r1,#0xc]
000064 ea43030c ORR r3,r3,r12
000068 f891c005 LDRB r12,[r1,#5]
00006c ea42024c ORR r2,r2,r12,LSL #1
000070 431a ORRS r2,r2,r3
;;;196 ((u32)ADC_InitStruct->ADC_ContinuousConvMode << 1));
;;;197 /* Write to ADCx CR2 */
;;;198 ADCx->CR2 = tmpreg1;
000072 6082 STR r2,[r0,#8]
;;;199
;;;200 /*---------------------------- ADCx SQR1 Configuration -----------------*/
;;;201 /* Get the ADCx SQR1 value */
;;;202 tmpreg1 = ADCx->SQR1;
000074 6ac2 LDR r2,[r0,#0x2c]
;;;203 /* Clear L bits */
;;;204 tmpreg1 &= SQR1_CLEAR_Mask;
000076 f4220270 BIC r2,r2,#0xf00000
;;;205 /* Configure ADCx: regular channel sequence length */
;;;206 /* Set L bits according to ADC_NbrOfChannel value */
;;;207 tmpreg2 |= (ADC_InitStruct->ADC_NbrOfChannel - 1);
00007a 7c09 LDRB r1,[r1,#0x10]
00007c 1e49 SUBS r1,r1,#1
00007e b2c9 UXTB r1,r1
;;;208 tmpreg1 |= ((u32)tmpreg2 << 20);
000080 ea425101 ORR r1,r2,r1,LSL #20
;;;209 /* Write to ADCx SQR1 */
;;;210 ADCx->SQR1 = tmpreg1;
000084 62c1 STR r1,[r0,#0x2c]
;;;211 }
000086 4770 BX lr
;;;212
ENDP
ADC_StructInit PROC
;;;224 /* Initialize the ADC_Mode member */
;;;225 ADC_InitStruct->ADC_Mode = ADC_Mode_Independent;
000088 2100 MOVS r1,#0
00008a 6001 STR r1,[r0,#0]
;;;226
;;;227 /* initialize the ADC_ScanConvMode member */
;;;228 ADC_InitStruct->ADC_ScanConvMode = DISABLE;
00008c 7101 STRB r1,[r0,#4]
;;;229
;;;230 /* Initialize the ADC_ContinuousConvMode member */
;;;231 ADC_InitStruct->ADC_ContinuousConvMode = DISABLE;
00008e 7141 STRB r1,[r0,#5]
;;;232
;;;233 /* Initialize the ADC_ExternalTrigConv member */
;;;234 ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1;
000090 6081 STR r1,[r0,#8]
;;;235
;;;236 /* Initialize the ADC_DataAlign member */
;;;237 ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;
000092 60c1 STR r1,[r0,#0xc]
;;;238
;;;239 /* Initialize the ADC_NbrOfChannel member */
;;;240 ADC_InitStruct->ADC_NbrOfChannel = 1;
000094 2101 MOVS r1,#1
000096 7401 STRB r1,[r0,#0x10]
;;;241 }
000098 4770 BX lr
;;;242
ENDP
ADC_Cmd PROC
;;;256
;;;257 if (NewState != DISABLE)
00009a b121 CBZ r1,|L1.166|
;;;258 {
;;;259 /* Set the ADON bit to wake up the ADC from power down mode */
;;;260 ADCx->CR2 |= CR2_ADON_Set;
00009c 6881 LDR r1,[r0,#8]
00009e f0410101 ORR r1,r1,#1
0000a2 6081 STR r1,[r0,#8]
;;;261 }
;;;262 else
;;;263 {
;;;264 /* Disable the selected ADC peripheral */
;;;265 ADCx->CR2 &= CR2_ADON_Reset;
;;;266 }
;;;267 }
0000a4 4770 BX lr
|L1.166|
0000a6 6881 LDR r1,[r0,#8] ;265
0000a8 f0210101 BIC r1,r1,#1 ;265
0000ac 6081 STR r1,[r0,#8] ;265
0000ae 4770 BX lr
;;;268
ENDP
ADC_DMACmd PROC
;;;282
;;;283 if (NewState != DISABLE)
0000b0 b121 CBZ r1,|L1.188|
;;;284 {
;;;285 /* Enable the selected ADC DMA request */
;;;286 ADCx->CR2 |= CR2_DMA_Set;
0000b2 6881 LDR r1,[r0,#8]
0000b4 f4417180 ORR r1,r1,#0x100
0000b8 6081 STR r1,[r0,#8]
;;;287 }
;;;288 else
;;;289 {
;;;290 /* Disable the selected ADC DMA request */
;;;291 ADCx->CR2 &= CR2_DMA_Reset;
;;;292 }
;;;293 }
0000ba 4770 BX lr
|L1.188|
0000bc 6881 LDR r1,[r0,#8] ;291
0000be f64f62ff MOV r2,#0xfeff ;291
0000c2 4011 ANDS r1,r1,r2 ;291
0000c4 6081 STR r1,[r0,#8] ;291
0000c6 4770 BX lr
;;;294
ENDP
ADC_ITConfig PROC
;;;318 /* Get the ADC IT index */
;;;319 itmask = (u8)ADC_IT;
0000c8 b2c9 UXTB r1,r1
;;;320
;;;321 if (NewState != DISABLE)
0000ca b11a CBZ r2,|L1.212|
;;;322 {
;;;323 /* Enable the selected ADC interrupts */
;;;324 ADCx->CR1 |= itmask;
0000cc 6842 LDR r2,[r0,#4]
0000ce 4311 ORRS r1,r1,r2
0000d0 6041 STR r1,[r0,#4]
;;;325 }
;;;326 else
;;;327 {
;;;328 /* Disable the selected ADC interrupts */
;;;329 ADCx->CR1 &= (~(u32)itmask);
;;;330 }
;;;331 }
0000d2 4770 BX lr
|L1.212|
0000d4 6842 LDR r2,[r0,#4] ;329
0000d6 ea220101 BIC r1,r2,r1 ;329
0000da 6041 STR r1,[r0,#4] ;329
0000dc 4770 BX lr
;;;332
ENDP
ADC_ResetCalibration PROC
;;;342 /* Resets the selected ADC calibartion registers */
;;;343 ADCx->CR2 |= CR2_RSTCAL_Set;
0000de 6881 LDR r1,[r0,#8]
0000e0 f0410108 ORR r1,r1,#8
0000e4 6081 STR r1,[r0,#8]
;;;344 }
0000e6 4770 BX lr
;;;345
ENDP
ADC_GetResetCalibrationStatus PROC
;;;353 FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx)
;;;354 {
0000e8 4601 MOV r1,r0
;;;355 FlagStatus bitstatus = RESET;
0000ea 2000 MOVS r0,#0
;;;356
;;;357 /* Check the status of RSTCAL bit */
;;;358 if ((ADCx->CR2 & CR2_RSTCAL_Set) != (u16)RESET)
0000ec 6889 LDR r1,[r1,#8]
0000ee f0110f08 TST r1,#8
0000f2 d000 BEQ |L1.246|
;;;359 {
;;;360 /* RSTCAL bit is set */
;;;361 bitstatus = SET;
0000f4 2001 MOVS r0,#1
|L1.246|
;;;362 }
;;;363 else
;;;364 {
;;;365 /* RSTCAL bit is reset */
;;;366 bitstatus = RESET;
;;;367 }
;;;368 /* Return the RSTCAL bit status */
;;;369 return bitstatus;
;;;370 }
0000f6 4770 BX lr
;;;371
ENDP
ADC_StartCalibration PROC
;;;381 /* Enable the selected ADC calibration process */
;;;382 ADCx->CR2 |= CR2_CAL_Set;
0000f8 6881 LDR r1,[r0,#8]
0000fa f0410104 ORR r1,r1,#4
0000fe 6081 STR r1,[r0,#8]
;;;383 }
000100 4770 BX lr
;;;384
ENDP
ADC_GetCalibrationStatus PROC
;;;392 FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx)
;;;393 {
000102 4601 MOV r1,r0
;;;394 FlagStatus bitstatus = RESET;
000104 2000 MOVS r0,#0
;;;395
;;;396 /* Check the status of CAL bit */
;;;397 if ((ADCx->CR2 & CR2_CAL_Set) != (u16)RESET)
000106 6889 LDR r1,[r1,#8]
000108 f0110f04 TST r1,#4
00010c d000 BEQ |L1.272|
;;;398 {
;;;399 /* CAL bit is set: calibration on going */
;;;400 bitstatus = SET;
00010e 2001 MOVS r0,#1
|L1.272|
;;;401 }
;;;402 else
;;;403 {
;;;404 /* CAL bit is reset: end of calibration */
;;;405 bitstatus = RESET;
;;;406 }
;;;407 /* Return the CAL bit status */
;;;408 return bitstatus;
;;;409 }
000110 4770 BX lr
;;;410
ENDP
ADC_SoftwareStartConvCmd PROC
;;;424
;;;425 if (NewState != DISABLE)
000112 b121 CBZ r1,|L1.286|
;;;426 {
;;;427 /* Enable the selected ADC conversion on external event */
;;;428 /* Starts the selected ADC conversion */
;;;429 ADCx->CR2 |= CR2_EXTTRIG_SWSTRT_Set;
000114 6881 LDR r1,[r0,#8]
000116 f44101a0 ORR r1,r1,#0x500000
00011a 6081 STR r1,[r0,#8]
;;;430 }
;;;431 else
;;;432 {
;;;433 /* Stops the selected ADC conversion */
;;;434 /* Disable the selected ADC conversion on external event */
;;;435 ADCx->CR2 &= CR2_EXTTRIG_SWSTRT_Reset;
;;;436 }
;;;437 }
00011c 4770 BX lr
|L1.286|
00011e 6881 LDR r1,[r0,#8] ;435
000120 f42101a0 BIC r1,r1,#0x500000 ;435
000124 6081 STR r1,[r0,#8] ;435
000126 4770 BX lr
;;;438
ENDP
ADC_GetSoftwareStartConvStatus PROC
;;;446 FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx)
;;;447 {
000128 4601 MOV r1,r0
;;;448 FlagStatus bitstatus = RESET;
00012a 2000 MOVS r0,#0
;;;449
;;;450 /* Check the status of SWSTRT bit */
;;;451 if ((ADCx->CR2 & CR2_SWSTRT_Set) != (u32)RESET)
00012c 6889 LDR r1,[r1,#8]
00012e f4110f80 TST r1,#0x400000
000132 d000 BEQ |L1.310|
;;;452 {
;;;453 /* SWSTRT bit is set */
;;;454 bitstatus = SET;
000134 2001 MOVS r0,#1
|L1.310|
;;;455 }
;;;456 else
;;;457 {
;;;458 /* SWSTRT bit is reset */
;;;459 bitstatus = RESET;
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