📄 stm32f10x_gpio.txt
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; generated by ARM/Thumb C/C++ Compiler with , RVCT3.1 [Build 942] for uVision
; commandline ArmCC [--debug -c --asm --interleave -o.\rvmdk\stm32f10x_gpio.o --depend=.\rvmdk\stm32f10x_gpio.d --device=DARMSTM --apcs=interwork -O1 -Otime -I. -I..\BSP -I..\..\..\..\..\uCOS-II\Ports\arm-cortex-m3\Generic\RealView -I..\..\..\..\..\uCOS-II\Source -I..\..\..\..\..\CPU\ST\STM32\inc -I..\..\..\..\..\uC-CPU -I..\..\..\..\..\uC-CPU\Arm-Cortex-M3\RealView -I..\..\..\..\..\uC-LIB -I..\..\..\..\..\uC-Probe\Target\Plugins\uCOS-II -I..\..\..\..\..\uC-Probe\Target\Communication\Generic\Source -I..\..\..\..\..\uC-Probe\Target\Communication\Generic\RS-232\Ports\ST\STM32 -I..\..\..\..\..\uC-Probe\Target\Communication\Generic\RS-232\Source -IC:\Keil\ARM\INC\ST\STM32F10x ..\..\..\..\..\CPU\ST\STM32\src\stm32f10x_gpio.c]
THUMB
AREA ||.text||, CODE, READONLY, ALIGN=2
GPIO_DeInit PROC
;;;56 void GPIO_DeInit(GPIO_TypeDef* GPIOx)
;;;57 {
000000 b510 PUSH {r4,lr}
;;;58 switch (*(u32*)&GPIOx)
000002 4a8f LDR r2,|L1.576|
000004 1a81 SUBS r1,r0,r2
000006 4290 CMP r0,r2
000008 d02c BEQ |L1.100|
00000a dc11 BGT |L1.48|
00000c f1a04080 SUB r0,r0,#0x40000000
000010 f5b03084 SUBS r0,r0,#0x10800
000014 d01c BEQ |L1.80|
000016 f5b06f80 CMP r0,#0x400
00001a d137 BNE |L1.140|
;;;59 {
;;;60 case GPIOA_BASE:
;;;61 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE);
;;;62 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE);
;;;63 break;
;;;64
;;;65 case GPIOB_BASE:
;;;66 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE);
00001c 2101 MOVS r1,#1
00001e 2008 MOVS r0,#8
000020 f7fffffe BL RCC_APB2PeriphResetCmd
;;;67 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE);
000024 2100 MOVS r1,#0
000026 e8bd4010 POP {r4,lr}
00002a 2008 MOVS r0,#8
00002c f7ffbffe B.W RCC_APB2PeriphResetCmd
|L1.48|
000030 f5b16f80 CMP r1,#0x400 ;58
000034 d020 BEQ |L1.120|
000036 f5b16f00 CMP r1,#0x800 ;58
00003a d127 BNE |L1.140|
;;;68 break;
;;;69
;;;70 case GPIOC_BASE:
;;;71 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE);
;;;72 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE);
;;;73 break;
;;;74
;;;75 case GPIOD_BASE:
;;;76 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE);
;;;77 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE);
;;;78 break;
;;;79
;;;80 case GPIOE_BASE:
;;;81 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE);
00003c 2101 MOVS r1,#1
00003e 2040 MOVS r0,#0x40
000040 f7fffffe BL RCC_APB2PeriphResetCmd
;;;82 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE);
000044 2100 MOVS r1,#0
000046 e8bd4010 POP {r4,lr}
00004a 2040 MOVS r0,#0x40
00004c f7ffbffe B.W RCC_APB2PeriphResetCmd
|L1.80|
000050 2101 MOVS r1,#1 ;61
000052 2004 MOVS r0,#4 ;61
000054 f7fffffe BL RCC_APB2PeriphResetCmd
000058 2100 MOVS r1,#0 ;62
00005a e8bd4010 POP {r4,lr} ;62
00005e 2004 MOVS r0,#4 ;62
000060 f7ffbffe B.W RCC_APB2PeriphResetCmd
|L1.100|
000064 2101 MOVS r1,#1 ;71
000066 2010 MOVS r0,#0x10 ;71
000068 f7fffffe BL RCC_APB2PeriphResetCmd
00006c 2100 MOVS r1,#0 ;72
00006e e8bd4010 POP {r4,lr} ;72
000072 2010 MOVS r0,#0x10 ;72
000074 f7ffbffe B.W RCC_APB2PeriphResetCmd
|L1.120|
000078 2101 MOVS r1,#1 ;76
00007a 2020 MOVS r0,#0x20 ;76
00007c f7fffffe BL RCC_APB2PeriphResetCmd
000080 2100 MOVS r1,#0 ;77
000082 e8bd4010 POP {r4,lr} ;77
000086 2020 MOVS r0,#0x20 ;77
000088 f7ffbffe B.W RCC_APB2PeriphResetCmd
|L1.140|
;;;83 break;
;;;84
;;;85 default:
;;;86 break;
;;;87 }
;;;88 }
00008c bd10 POP {r4,pc}
;;;89
ENDP
GPIO_AFIODeInit PROC
;;;99 void GPIO_AFIODeInit(void)
;;;100 {
00008e b510 PUSH {r4,lr}
;;;101 RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE);
000090 2101 MOVS r1,#1
000092 4608 MOV r0,r1
000094 f7fffffe BL RCC_APB2PeriphResetCmd
;;;102 RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE);
000098 2100 MOVS r1,#0
00009a e8bd4010 POP {r4,lr}
00009e 2001 MOVS r0,#1
0000a0 f7ffbffe B.W RCC_APB2PeriphResetCmd
;;;103 }
;;;104
ENDP
GPIO_Init PROC
;;;116 void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
;;;117 {
0000a4 e92d01f0 PUSH {r4-r8}
;;;118 u32 currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00;
0000a8 2200 MOVS r2,#0
;;;119 u32 tmpreg = 0x00, pinmask = 0x00;
;;;120
;;;121 /* Check the parameters */
;;;122 assert(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
;;;123 assert(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
;;;124
;;;125 /*---------------------------- GPIO Mode Configuration -----------------------*/
;;;126 currentmode = ((u32)GPIO_InitStruct->GPIO_Mode) & ((u32)0x0F);
0000aa f891c003 LDRB r12,[r1,#3]
0000ae f00c030f AND r3,r12,#0xf
;;;127
;;;128 if ((((u32)GPIO_InitStruct->GPIO_Mode) & ((u32)0x10)) != 0x00)
0000b2 f01c0f10 TST r12,#0x10
0000b6 d003 BEQ |L1.192|
;;;129 {
;;;130 /* Check the parameters */
;;;131 assert(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
;;;132 /* Output mode */
;;;133 currentmode |= (u32)GPIO_InitStruct->GPIO_Speed;
0000b8 f891c002 LDRB r12,[r1,#2]
0000bc ea4c0303 ORR r3,r12,r3
|L1.192|
;;;134 }
;;;135
;;;136 /*---------------------------- GPIO CRL Configuration ------------------------*/
;;;137 /* Configure the eight low port pins */
;;;138 if (((u32)GPIO_InitStruct->GPIO_Pin & ((u32)0x00FF)) != 0x00)
0000c0 f8b1c000 LDRH r12,[r1,#0]
0000c4 f04f060f MOV r6,#0xf
0000c8 f01c0fff TST r12,#0xff
0000cc f04f0701 MOV r7,#1
0000d0 d01d BEQ |L1.270|
;;;139 {
;;;140 tmpreg = GPIOx->CRL;
0000d2 6804 LDR r4,[r0,#0]
|L1.212|
;;;141
;;;142 for (pinpos = 0x00; pinpos < 0x08; pinpos++)
;;;143 {
;;;144 pos = ((u32)0x01) << pinpos;
0000d4 fa07fc02 LSL r12,r7,r2
;;;145 /* Get the port pins position */
;;;146 currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
0000d8 880d LDRH r5,[r1,#0]
0000da ea05050c AND r5,r5,r12
;;;147
;;;148 if (currentpin == pos)
0000de 4565 CMP r5,r12
0000e0 d111 BNE |L1.262|
;;;149 {
;;;150 pos = pinpos << 2;
0000e2 0095 LSLS r5,r2,#2
;;;151 /* Clear the corresponding low control register bits */
;;;152 pinmask = ((u32)0x0F) << pos;
0000e4 fa06f805 LSL r8,r6,r5
;;;153 tmpreg &= ~pinmask;
0000e8 ea240408 BIC r4,r4,r8
;;;154
;;;155 /* Write the mode configuration in the corresponding bits */
;;;156 tmpreg |= (currentmode << pos);
0000ec fa03f505 LSL r5,r3,r5
0000f0 432c ORRS r4,r4,r5
;;;157
;;;158 /* Reset the corresponding ODR bit */
;;;159 if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
0000f2 78cd LDRB r5,[r1,#3]
0000f4 2d28 CMP r5,#0x28
0000f6 d101 BNE |L1.252|
;;;160 {
;;;161 GPIOx->BRR = (((u32)0x01) << pinpos);
0000f8 f8c0c014 STR r12,[r0,#0x14]
|L1.252|
;;;162 }
;;;163 /* Set the corresponding ODR bit */
;;;164 if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
0000fc 78cd LDRB r5,[r1,#3]
0000fe 2d48 CMP r5,#0x48
000100 d101 BNE |L1.262|
;;;165 {
;;;166 GPIOx->BSRR = (((u32)0x01) << pinpos);
000102 f8c0c010 STR r12,[r0,#0x10]
|L1.262|
000106 1c52 ADDS r2,r2,#1 ;142
000108 2a08 CMP r2,#8 ;142
00010a d3e3 BCC |L1.212|
;;;167 }
;;;168 }
;;;169 }
;;;170 GPIOx->CRL = tmpreg;
00010c 6004 STR r4,[r0,#0]
|L1.270|
;;;171 tmpreg = 0;
;;;172 }
;;;173
;;;174 /*---------------------------- GPIO CRH Configuration ------------------------*/
;;;175 /* Configure the eight high port pins */
;;;176 if (GPIO_InitStruct->GPIO_Pin > 0x00FF)
00010e 880a LDRH r2,[r1,#0]
000110 2aff CMP r2,#0xff
000112 d920 BLS |L1.342|
;;;177 {
;;;178 tmpreg = GPIOx->CRH;
000114 6844 LDR r4,[r0,#4]
;;;179 for (pinpos = 0x00; pinpos < 0x08; pinpos++)
000116 2200 MOVS r2,#0
|L1.280|
;;;180 {
;;;181 pos = (((u32)0x01) << (pinpos + 0x08));
000118 f1020c08 ADD r12,r2,#8
00011c fa07fc0c LSL r12,r7,r12
;;;182 /* Get the port pins position */
;;;183 currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos);
000120 880d LDRH r5,[r1,#0]
000122 ea05050c AND r5,r5,r12
;;;184 if (currentpin == pos)
000126 4565 CMP r5,r12
000128 d111 BNE |L1.334|
;;;185 {
;;;186 pos = pinpos << 2;
00012a 0095 LSLS r5,r2,#2
;;;187 /* Clear the corresponding high control register bits */
;;;188 pinmask = ((u32)0x0F) << pos;
00012c fa06f805 LSL r8,r6,r5
;;;189 tmpreg &= ~pinmask;
000130 ea240408 BIC r4,r4,r8
;;;190
;;;191 /* Write the mode configuration in the corresponding bits */
;;;192 tmpreg |= (currentmode << pos);
000134 fa03f505 LSL r5,r3,r5
000138 432c ORRS r4,r4,r5
;;;193
;;;194 /* Reset the corresponding ODR bit */
;;;195 if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
00013a 78cd LDRB r5,[r1,#3]
00013c 2d28 CMP r5,#0x28
00013e d101 BNE |L1.324|
;;;196 {
;;;197 GPIOx->BRR = (((u32)0x01) << (pinpos + 0x08));
000140 f8c0c014 STR r12,[r0,#0x14]
|L1.324|
;;;198 }
;;;199 /* Set the corresponding ODR bit */
;;;200 if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
000144 78cd LDRB r5,[r1,#3]
000146 2d48 CMP r5,#0x48
000148 d101 BNE |L1.334|
;;;201 {
;;;202 GPIOx->BSRR = (((u32)0x01) << (pinpos + 0x08));
00014a f8c0c010 STR r12,[r0,#0x10]
|L1.334|
00014e 1c52 ADDS r2,r2,#1 ;179
000150 2a08 CMP r2,#8 ;179
000152 d3e1 BCC |L1.280|
;;;203 }
;;;204 }
;;;205 }
;;;206 GPIOx->CRH = tmpreg;
000154 6044 STR r4,[r0,#4]
|L1.342|
;;;207 }
;;;208 }
000156 e8bd01f0 POP {r4-r8}
00015a 4770 BX lr
;;;209
ENDP
GPIO_StructInit PROC
;;;220 /* Reset GPIO init structure parameters values */
;;;221 GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
00015c f64f71ff MOV r1,#0xffff
000160 8001 STRH r1,[r0,#0]
;;;222 GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
000162 2102 MOVS r1,#2
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