📄 stm32f10x_adc.lst
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\ 00000000 8068 LDR R0,[R0, #+8]
452 {
453 /* SWSTRT bit is set */
454 bitstatus = SET;
455 }
456 else
457 {
458 /* SWSTRT bit is reset */
459 bitstatus = RESET;
\ 00000002 4002 LSLS R0,R0,#+9
\ 00000004 01D5 BPL.N ??ADC_GetSoftwareStartConvStatus_0
\ 00000006 0120 MOVS R0,#+1
\ 00000008 7047 BX LR
\ ??ADC_GetSoftwareStartConvStatus_0:
\ 0000000A 0020 MOVS R0,#+0
460 }
461 /* Return the SWSTRT bit status */
462 return bitstatus;
\ 0000000C 7047 BX LR ;; return
463 }
464
465 /*******************************************************************************
466 * Function Name : ADC_DiscModeChannelCountConfig
467 * Description : Configures the discontinuous mode for the selected ADC regular
468 * group channel.
469 * Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
470 * - Number: specifies the discontinuous mode regular channel
471 * count value. This number must be between 1 and 8.
472 * Output : None
473 * Return : None
474 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
475 void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, u8 Number)
476 {
477 u32 tmpreg1 = 0;
478 u8 tmpreg2 = 0;
479
480 /* Check the parameters */
481 assert(IS_ADC_REGULAR_DISC_NUMBER(Number));
482
483 /* Get the old register value */
484 tmpreg1 = ADCx->CR1;
\ ADC_DiscModeChannelCountConfig:
\ 00000000 4268 LDR R2,[R0, #+4]
485 /* Clear the old discontinuous mode channel count */
486 tmpreg1 &= CR1_DISCNUM_Reset;
487 /* Set the discontinuous mode channel count */
488 tmpreg2 = Number - 1;
489 tmpreg1 |= ((u32)tmpreg2 << 13);
490 /* Store the new register value */
491 ADCx->CR1 = tmpreg1;
\ 00000002 7FF46043 MVNS R3,#+57344
\ 00000006 1340 ANDS R3,R3,R2
\ 00000008 491E SUBS R1,R1,#+1
\ 0000000A C9B2 UXTB R1,R1
\ 0000000C 53EA4131 ORRS R1,R3,R1, LSL #+13
\ 00000010 4160 STR R1,[R0, #+4]
492 }
\ 00000012 7047 BX LR ;; return
493
494 /*******************************************************************************
495 * Function Name : ADC_DiscModeCmd
496 * Description : Enables or disables the discontinuous mode on regular group
497 * channel for the specified ADC
498 * Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
499 * - NewState: new state of the selected ADC discontinuous mode
500 * on regular group channel.
501 * This parameter can be: ENABLE or DISABLE.
502 * Output : None
503 * Return : None
504 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
505 void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
506 {
507 /* Check the parameters */
508 assert(IS_FUNCTIONAL_STATE(NewState));
509
510 if (NewState != DISABLE)
\ ADC_DiscModeCmd:
\ 00000000 0029 CMP R1,#+0
\ 00000002 4168 LDR R1,[R0, #+4]
\ 00000004 03D0 BEQ.N ??ADC_DiscModeCmd_0
511 {
512 /* Enable the selected ADC regular discontinuous mode */
513 ADCx->CR1 |= CR1_DISCEN_Set;
\ 00000006 51F40061 ORRS R1,R1,#0x800
\ 0000000A 4160 STR R1,[R0, #+4]
\ 0000000C 7047 BX LR
514 }
515 else
516 {
517 /* Disable the selected ADC regular discontinuous mode */
518 ADCx->CR1 &= CR1_DISCEN_Reset;
\ ??ADC_DiscModeCmd_0:
\ 0000000E 7FF40062 MVNS R2,#+2048
\ 00000012 0A40 ANDS R2,R2,R1
\ 00000014 4260 STR R2,[R0, #+4]
519 }
520 }
\ 00000016 7047 BX LR ;; return
521
522 /*******************************************************************************
523 * Function Name : ADC_RegularChannelConfig
524 * Description : Configures for the selected ADC regular channel its corresponding
525 * rank in the sequencer and its sample time.
526 * Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
527 * - ADC_Channel: the ADC channel to configure.
528 * This parameter can be one of the following values:
529 * - ADC_Channel_0: ADC Channel0 selected
530 * - ADC_Channel_1: ADC Channel1 selected
531 * - ADC_Channel_2: ADC Channel2 selected
532 * - ADC_Channel_3: ADC Channel3 selected
533 * - ADC_Channel_4: ADC Channel4 selected
534 * - ADC_Channel_5: ADC Channel5 selected
535 * - ADC_Channel_6: ADC Channel6 selected
536 * - ADC_Channel_7: ADC Channel7 selected
537 * - ADC_Channel_8: ADC Channel8 selected
538 * - ADC_Channel_9: ADC Channel9 selected
539 * - ADC_Channel_10: ADC Channel10 selected
540 * - ADC_Channel_11: ADC Channel11 selected
541 * - ADC_Channel_12: ADC Channel12 selected
542 * - ADC_Channel_13: ADC Channel13 selected
543 * - ADC_Channel_14: ADC Channel14 selected
544 * - ADC_Channel_15: ADC Channel15 selected
545 * - ADC_Channel_16: ADC Channel16 selected
546 * - ADC_Channel_17: ADC Channel17 selected
547 * - Rank: The rank in the regular group sequencer. This parameter
548 * must be between 1 to 16.
549 * - ADC_SampleTime: The sample time value to be set for the
550 * selected channel.
551 * This parameter can be one of the following values:
552 * - ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles
553 * - ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles
554 * - ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles
555 * - ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles
556 * - ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles
557 * - ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles
558 * - ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles
559 * - ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles
560 * Output : None
561 * Return : None
562 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
563 void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel, u8 Rank, u8 ADC_SampleTime)
564 {
\ ADC_RegularChannelConfig:
\ 00000000 70B5 PUSH {R4-R6,LR}
565 u32 tmpreg1 = 0, tmpreg2 = 0;
566
567 /* Check the parameters */
568 assert(IS_ADC_CHANNEL(ADC_Channel));
569 assert(IS_ADC_REGULAR_RANK(Rank));
570 assert(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
571
572 /* if ADC_Channel_10 ... ADC_Channel_17 is selected */
573 if (ADC_Channel > ADC_Channel_9)
\ 00000002 0A29 CMP R1,#+10
\ 00000004 0CD3 BCC.N ??ADC_RegularChannelConfig_0
574 {
575 /* Get the old register value */
576 tmpreg1 = ADCx->SMPR1;
\ 00000006 C468 LDR R4,[R0, #+12]
577 /* Calculate the mask to clear */
578 tmpreg2 = (u32)SMPR1_SMP_Set << (3 * (ADC_Channel - 10));
579 /* Clear the old discontinuous mode channel count */
580 tmpreg1 &= ~tmpreg2;
581 /* Calculate the mask to set */
582 tmpreg2 = (u32)ADC_SampleTime << (3 * (ADC_Channel - 10));
583 /* Set the discontinuous mode channel count */
584 tmpreg1 |= tmpreg2;
585 /* Store the new register value */
586 ADCx->SMPR1 = tmpreg1;
\ 00000008 0D00 MOVS R5,R1
\ 0000000A F635 ADDS R5,R5,#+246
\ 0000000C 0326 MOVS R6,#+3
\ 0000000E 05FB06F5 MUL R5,R5,R6
\ 00000012 0726 MOVS R6,#+7
\ 00000014 AE40 LSLS R6,R6,R5
\ 00000016 B443 BICS R4,R4,R6
\ 00000018 AB40 LSLS R3,R3,R5
\ 0000001A 2343 ORRS R3,R3,R4
\ 0000001C C360 STR R3,[R0, #+12]
\ 0000001E 09E0 B.N ??ADC_RegularChannelConfig_1
587 }
588 else /* ADC_Channel include in ADC_Channel_[0..9] */
589 {
590 /* Get the old register value */
591 tmpreg1 = ADCx->SMPR2;
\ ??ADC_RegularChannelConfig_0:
\ 00000020 0469 LDR R4,[R0, #+16]
592 /* Calculate the mask to clear */
593 tmpreg2 = (u32)SMPR2_SMP_Set << (3 * ADC_Channel);
594 /* Clear the old discontinuous mode channel count */
595 tmpreg1 &= ~tmpreg2;
596 /* Calculate the mask to set */
597 tmpreg2 = (u32)ADC_SampleTime << (3 * ADC_Channel);
598 /* Set the discontinuous mode channel count */
599 tmpreg1 |= tmpreg2;
600 /* Store the new register value */
601 ADCx->SMPR2 = tmpreg1;
\ 00000022 0325 MOVS R5,#+3
\ 00000024 01FB05F5 MUL R5,R1,R5
\ 00000028 0726 MOVS R6,#+7
\ 0000002A AE40 LSLS R6,R6,R5
\ 0000002C B443 BICS R4,R4,R6
\ 0000002E AB40 LSLS R3,R3,R5
\ 00000030 2343 ORRS R3,R3,R4
\ 00000032 0361 STR R3,[R0, #+16]
602 }
603 /* For Rank 1 to 6 */
604 if (Rank < 7)
\ ??ADC_RegularChannelConfig_1:
\ 00000034 072A CMP R2,#+7
\ 00000036 0BD2 BCS.N ??ADC_RegularChannelConfig_2
605 {
606 /* Get the old register value */
607 tmpreg1 = ADCx->SQR3;
\ 00000038 436B LDR R3,[R0, #+52]
608 /* Calculate the mask to clear */
609 tmpreg2 = (u32)SQR3_SQ_Set << (5 * (Rank - 1));
610 /* Clear the old SQx bits for the selected rank */
611 tmpreg1 &= ~tmpreg2;
612 /* Calculate the mask to set */
613 tmpreg2 = (u32)ADC_Channel << (5 * (Rank - 1));
614 /* Set the SQx bits for the selected rank */
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