📄 stm32f10x_rcc.lst
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618 * Output : None
619 * Return : None
620 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
621 void RCC_LSICmd(FunctionalState NewState)
622 {
623 /* Check the parameters */
624 assert(IS_FUNCTIONAL_STATE(NewState));
625
626 *(vu32 *) CSR_LSION_BB = (u32)NewState;
\ RCC_LSICmd:
\ 00000000 0149 LDR.N R1,??RCC_LSICmd_0 ;; 0x42420480
\ 00000002 0860 STR R0,[R1, #+0]
627 }
\ 00000004 7047 BX LR ;; return
\ 00000006 00BF Nop
\ ??RCC_LSICmd_0:
\ 00000008 80044242 DC32 0x42420480
628
629 /*******************************************************************************
630 * Function Name : RCC_RTCCLKConfig
631 * Description : Configures the RTC clock (RTCCLK).
632 * Once the RTC clock is selected it can抰 be changed unless the
633 * Backup domain is reset.
634 * Input : - RCC_RTCCLKSource: specifies the RTC clock source.
635 * This parameter can be one of the following values:
636 * - RCC_RTCCLKSource_LSE: LSE selected as RTC clock
637 * - RCC_RTCCLKSource_LSI: LSI selected as RTC clock
638 * - RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128
639 * selected as RTC clock
640 * Output : None
641 * Return : None
642 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
643 void RCC_RTCCLKConfig(u32 RCC_RTCCLKSource)
644 {
645 /* Check the parameters */
646 assert(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
647
648 /* Select the RTC clock source */
649 RCC->BDCR |= RCC_RTCCLKSource;
\ RCC_RTCCLKConfig:
\ 00000000 .... LDR.N R1,??DataTable17 ;; 0x40021020
\ 00000002 0A68 LDR R2,[R1, #+0]
\ 00000004 1043 ORRS R0,R0,R2
\ 00000006 0860 STR R0,[R1, #+0]
650 }
\ 00000008 7047 BX LR ;; return
651
652 /*******************************************************************************
653 * Function Name : RCC_RTCCLKCmd
654 * Description : Enables or disables the RTC clock.
655 * This function must be used only after the RTC clock was
656 * selected using the RCC_RTCCLKConfig function.
657 * Input : - NewState: new state of the RTC clock.
658 * This parameter can be: ENABLE or DISABLE.
659 * Output : None
660 * Return : None
661 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
662 void RCC_RTCCLKCmd(FunctionalState NewState)
663 {
664 /* Check the parameters */
665 assert(IS_FUNCTIONAL_STATE(NewState));
666
667 *(vu32 *) BDCR_RTCEN_BB = (u32)NewState;
\ RCC_RTCCLKCmd:
\ 00000000 0149 LDR.N R1,??RCC_RTCCLKCmd_0 ;; 0x4242043c
\ 00000002 0860 STR R0,[R1, #+0]
668 }
\ 00000004 7047 BX LR ;; return
\ 00000006 00BF Nop
\ ??RCC_RTCCLKCmd_0:
\ 00000008 3C044242 DC32 0x4242043c
669
670 /*******************************************************************************
671 * Function Name : RCC_GetClocksFreq
672 * Description : Returns the frequencies of different on chip clocks.
673 * Input : - RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which
674 * will hold the clocks frequencies.
675 * Output : None
676 * Return : None
677 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
678 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
679 {
\ RCC_GetClocksFreq:
\ 00000000 30B5 PUSH {R4,R5,LR}
680 u32 tmp = 0, pllmull = 0, pllsource = 0, presc = 0;
681
682 /* Get SYSCLK source -------------------------------------------------------*/
683 tmp = RCC->CFGR & CFGR_SWS_Mask;
\ 00000002 .... LDR.N R1,??DataTable14 ;; 0x40021004
\ 00000004 0A68 LDR R2,[R1, #+0]
\ 00000006 12F00C03 ANDS R3,R2,#0xC
684
685 switch (tmp)
\ 0000000A 204A LDR.N R2,??RCC_GetClocksFreq_0 ;; 0x7a1200
\ 0000000C 082B CMP R3,#+8
\ 0000000E 01D0 BEQ.N ??RCC_GetClocksFreq_1
686 {
687 case 0x00: /* HSI used as system clock */
688 RCC_Clocks->SYSCLK_Frequency = HSI_Value;
\ 00000010 0260 STR R2,[R0, #+0]
\ 00000012 16E0 B.N ??RCC_GetClocksFreq_2
689 break;
690
691 case 0x04: /* HSE used as system clock */
692 RCC_Clocks->SYSCLK_Frequency = HSE_Value;
693 break;
694
695 case 0x08: /* PLL used as system clock */
696 /* Get PLL clock source and multiplication factor ----------------------*/
697 pllmull = RCC->CFGR & CFGR_PLLMull_Mask;
\ ??RCC_GetClocksFreq_1:
\ 00000014 0B68 LDR R3,[R1, #+0]
\ 00000016 13F47013 ANDS R3,R3,#0x3C0000
698 pllmull = ( pllmull >> 18) + 2;
\ 0000001A 9B0C LSRS R3,R3,#+18
\ 0000001C 9B1C ADDS R3,R3,#+2
699
700 pllsource = RCC->CFGR & CFGR_PLLSRC_Mask;
\ 0000001E 0D68 LDR R5,[R1, #+0]
\ 00000020 5FF48034 MOVS R4,#+65536
\ 00000024 2C40 ANDS R4,R4,R5
701
702 if (pllsource == 0x00)
\ 00000026 03D1 BNE.N ??RCC_GetClocksFreq_3
703 {/* HSI oscillator clock divided by 2 selected as PLL clock entry */
704 RCC_Clocks->SYSCLK_Frequency = (HSI_Value >> 1) * pllmull;
\ 00000028 5208 LSRS R2,R2,#+1
\ 0000002A 5343 MULS R3,R2,R3
\ 0000002C 0360 STR R3,[R0, #+0]
\ 0000002E 08E0 B.N ??RCC_GetClocksFreq_2
705 }
706 else
707 {/* HSE selected as PLL clock entry */
708
709 if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (u32)RESET)
\ ??RCC_GetClocksFreq_3:
\ 00000030 0C68 LDR R4,[R1, #+0]
\ 00000032 A403 LSLS R4,R4,#+14
\ 00000034 03D5 BPL.N ??RCC_GetClocksFreq_4
710 {/* HSE oscillator clock divided by 2 */
711
712 RCC_Clocks->SYSCLK_Frequency = (HSE_Value >> 1) * pllmull;
\ 00000036 5208 LSRS R2,R2,#+1
\ 00000038 5343 MULS R3,R2,R3
\ 0000003A 0360 STR R3,[R0, #+0]
\ 0000003C 01E0 B.N ??RCC_GetClocksFreq_2
713 }
714 else
715 {
716 RCC_Clocks->SYSCLK_Frequency = HSE_Value * pllmull;
\ ??RCC_GetClocksFreq_4:
\ 0000003E 5343 MULS R3,R2,R3
\ 00000040 0360 STR R3,[R0, #+0]
717 }
718 }
719 break;
720
721 default:
722 RCC_Clocks->SYSCLK_Frequency = HSI_Value;
723 break;
724 }
725
726 /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/
727 /* Get HCLK prescaler */
728 tmp = RCC->CFGR & CFGR_HPRE_Set_Mask;
\ ??RCC_GetClocksFreq_2:
\ 00000042 0A68 LDR R2,[R1, #+0]
\ 00000044 12F0F003 ANDS R3,R2,#0xF0
729 tmp = tmp >> 4;
730 presc = APBAHBPrescTable[tmp];
731
732 /* HCLK clock frequency */
733 RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
\ 00000048 114A LDR.N R2,??RCC_GetClocksFreq_0+0x4 ;; APBAHBPrescTable
\ 0000004A 0468 LDR R4,[R0, #+0]
\ 0000004C 1B09 LSRS R3,R3,#+4
\ 0000004E D35C LDRB R3,[R2, R3]
\ 00000050 DC40 LSRS R4,R4,R3
\ 00000052 4460 STR R4,[R0, #+4]
734
735 /* Get PCLK1 prescaler */
736 tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask;
\ 00000054 0B68 LDR R3,[R1, #+0]
\ 00000056 13F4E063 ANDS R3,R3,#0x700
737 tmp = tmp >> 8;
738 presc = APBAHBPrescTable[tmp];
739
740 /* PCLK1 clock frequency */
741 RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
\ 0000005A 4468 LDR R4,[R0, #+4]
\ 0000005C 1B0A LSRS R3,R3,#+8
\ 0000005E D35C LDRB R3,[R2, R3]
\ 00000060 DC40 LSRS R4,R4,R3
\ 00000062 8460 STR R4,[R0, #+8]
742
743 /* Get PCLK2 prescaler */
744 tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask;
\ 00000064 0B68 LDR R3,[R1, #+0]
\ 00000066 13F46053 ANDS R3,R3,#0x3800
745 tmp = tmp >> 11;
746 presc = APBAHBPrescTable[tmp];
747
748 /* PCLK2 clock frequency */
749 RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
\ 0000006A 4468 LDR R4,[R0, #+4]
\ 0000006C DB0A LSRS R3,R3,#+11
\ 0000006E D35C LDRB R3,[R2, R3]
\ 00000070 DC40 LSRS R4,R4,R3
\ 00000072 C460 STR R4,[R0, #+12]
750
751 /* Get ADCCLK prescaler */
752 tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask;
\ 00000074 0968 LDR R1,[R1, #+0]
\ 00000076 11F44041 ANDS R1,R1,#0xC000
753 tmp = tmp >> 14;
754 presc = ADCPrescTable[tmp];
755
756 /* ADCCLK clock frequency */
757 RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;
\ 0000007A C368 LDR R3,[R0, #+12]
\ 0000007C 12EB9⌨️ 快捷键说明
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