📄 stm32f10x_rcc.lst
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452 * Description : Configures the High Speed APB clock (PCLK2).
453 * Input : - RCC_PCLK2: defines the APB2 clock. This clock is derived
454 * from the AHB clock (HCLK).
455 * This parameter can be one of the following values:
456 * - RCC_HCLK_Div1: APB2 clock = HCLK
457 * - RCC_HCLK_Div2: APB2 clock = HCLK/2
458 * - RCC_HCLK_Div4: APB2 clock = HCLK/4
459 * - RCC_HCLK_Div8: APB2 clock = HCLK/8
460 * - RCC_HCLK_Div16: APB2 clock = HCLK/16
461 * Output : None
462 * Return : None
463 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
464 void RCC_PCLK2Config(u32 RCC_PCLK2)
465 {
466 u32 tmpreg = 0;
467
468 /* Check the parameters */
469 assert(IS_RCC_PCLK(RCC_PCLK2));
470
471 tmpreg = RCC->CFGR;
\ RCC_PCLK2Config:
\ 00000000 .... LDR.N R1,??DataTable14 ;; 0x40021004
\ 00000002 0A68 LDR R2,[R1, #+0]
472
473 /* Clear PPRE2[13:11] bits */
474 tmpreg &= CFGR_PPRE2_Reset_Mask;
475
476 /* Set PPRE2[13:11] bits according to RCC_PCLK2 value */
477 tmpreg |= RCC_PCLK2 << 3;
478
479 /* Store the new value */
480 RCC->CFGR = tmpreg;
\ 00000004 7FF46053 MVNS R3,#+14336
\ 00000008 1340 ANDS R3,R3,R2
\ 0000000A 53EAC000 ORRS R0,R3,R0, LSL #+3
\ 0000000E 0860 STR R0,[R1, #+0]
481 }
\ 00000010 7047 BX LR ;; return
482
483 /*******************************************************************************
484 * Function Name : RCC_ITConfig
485 * Description : Enables or disables the specified RCC interrupts.
486 * Input : - RCC_IT: specifies the RCC interrupt sources to be enabled
487 * or disabled.
488 * This parameter can be any combination of the following values:
489 * - RCC_IT_LSIRDY: LSI ready interrupt
490 * - RCC_IT_LSERDY: LSE ready interrupt
491 * - RCC_IT_HSIRDY: HSI ready interrupt
492 * - RCC_IT_HSERDY: HSE ready interrupt
493 * - RCC_IT_PLLRDY: PLL ready interrupt
494 * - NewState: new state of the specified RCC interrupts.
495 * This parameter can be: ENABLE or DISABLE.
496 * Output : None
497 * Return : None
498 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
499 void RCC_ITConfig(u8 RCC_IT, FunctionalState NewState)
500 {
501 /* Check the parameters */
502 assert(IS_RCC_IT(RCC_IT));
503 assert(IS_FUNCTIONAL_STATE(NewState));
504
505 if (NewState != DISABLE)
\ RCC_ITConfig:
\ 00000000 044A LDR.N R2,??RCC_ITConfig_0 ;; 0x40021009
\ 00000002 0029 CMP R1,#+0
\ 00000004 1178 LDRB R1,[R2, #+0]
\ 00000006 02D0 BEQ.N ??RCC_ITConfig_1
506 {
507 /* Perform Byte access to RCC_CIR[12:8] bits to enable the selected interrupts */
508 *(vu8 *) 0x40021009 |= RCC_IT;
\ 00000008 0843 ORRS R0,R0,R1
\ 0000000A 1070 STRB R0,[R2, #+0]
\ 0000000C 7047 BX LR
509 }
510 else
511 {
512 /* Perform Byte access to RCC_CIR[12:8] bits to disable the selected interrupts */
513 *(vu8 *) 0x40021009 &= ~(u32)RCC_IT;
\ ??RCC_ITConfig_1:
\ 0000000E 8143 BICS R1,R1,R0
\ 00000010 1170 STRB R1,[R2, #+0]
514 }
515 }
\ 00000012 7047 BX LR ;; return
\ ??RCC_ITConfig_0:
\ 00000014 09100240 DC32 0x40021009
516
517 /*******************************************************************************
518 * Function Name : RCC_USBCLKConfig
519 * Description : Configures the USB clock (USBCLK).
520 * Input : - RCC_USBCLKSource: specifies the USB clock source. This clock
521 * is derived from the PLL output.
522 * This parameter can be one of the following values:
523 * - RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5
524 * selected as USB clock source
525 * - RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB
526 * clock source
527 * Output : None
528 * Return : None
529 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
530 void RCC_USBCLKConfig(u32 RCC_USBCLKSource)
531 {
532 /* Check the parameters */
533 assert(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource));
534
535 *(vu32 *) CFGR_USBPRE_BB = RCC_USBCLKSource;
\ RCC_USBCLKConfig:
\ 00000000 0149 LDR.N R1,??RCC_USBCLKConfig_0 ;; 0x424200d8
\ 00000002 0860 STR R0,[R1, #+0]
536 }
\ 00000004 7047 BX LR ;; return
\ 00000006 00BF Nop
\ ??RCC_USBCLKConfig_0:
\ 00000008 D8004242 DC32 0x424200d8
537
538 /*******************************************************************************
539 * Function Name : RCC_ADCCLKConfig
540 * Description : Configures the ADC clock (ADCCLK).
541 * Input : - RCC_ADCCLK: defines the ADC clock. This clock is derived
542 * from the APB2 clock (PCLK2).
543 * This parameter can be one of the following values:
544 * - RCC_PCLK2_Div2: ADC clock = PCLK2/2
545 * - RCC_PCLK2_Div4: ADC clock = PCLK2/4
546 * - RCC_PCLK2_Div6: ADC clock = PCLK2/6
547 * - RCC_PCLK2_Div8: ADC clock = PCLK2/8
548 * Output : None
549 * Return : None
550 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
551 void RCC_ADCCLKConfig(u32 RCC_ADCCLK)
552 {
553 u32 tmpreg = 0;
554
555 /* Check the parameters */
556 assert(IS_RCC_ADCCLK(RCC_ADCCLK));
557
558 tmpreg = RCC->CFGR;
\ RCC_ADCCLKConfig:
\ 00000000 .... LDR.N R1,??DataTable14 ;; 0x40021004
\ 00000002 0A68 LDR R2,[R1, #+0]
559
560 /* Clear ADCPRE[15:14] bits */
561 tmpreg &= CFGR_ADCPRE_Reset_Mask;
562
563 /* Set ADCPRE[15:14] bits according to RCC_ADCCLK value */
564 tmpreg |= RCC_ADCCLK;
565
566 /* Store the new value */
567 RCC->CFGR = tmpreg;
\ 00000004 7FF44043 MVNS R3,#+49152
\ 00000008 1340 ANDS R3,R3,R2
\ 0000000A 1843 ORRS R0,R0,R3
\ 0000000C 0860 STR R0,[R1, #+0]
568 }
\ 0000000E 7047 BX LR ;; return
569
570 /*******************************************************************************
571 * Function Name : RCC_LSEConfig
572 * Description : Configures the External Low Speed oscillator (LSE).
573 * Input : - RCC_LSE: specifies the new state of the LSE.
574 * This parameter can be one of the following values:
575 * - RCC_LSE_OFF: LSE oscillator OFF
576 * - RCC_LSE_ON: LSE oscillator ON
577 * - RCC_LSE_Bypass: LSE oscillator bypassed with external
578 * clock
579 * Output : None
580 * Return : None
581 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
582 void RCC_LSEConfig(u32 RCC_LSE)
583 {
\ RCC_LSEConfig:
\ 00000000 00B5 PUSH {LR}
584 /* Check the parameters */
585 assert(IS_RCC_LSE(RCC_LSE));
586
587 /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
588 /* Reset LSEON bit */
589 *(vu8 *) BDCR_BASE = RCC_LSE_OFF;
\ 00000002 .... LDR.N R1,??DataTable17 ;; 0x40021020
\ 00000004 0022 MOVS R2,#+0
\ 00000006 0A70 STRB R2,[R1, #+0]
590
591 /* Reset LSEBYP bit */
592 *(vu8 *) BDCR_BASE = RCC_LSE_OFF;
\ 00000008 0A70 STRB R2,[R1, #+0]
593
594 /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */
595 switch(RCC_LSE)
\ 0000000A 0128 CMP R0,#+1
\ 0000000C 02D0 BEQ.N ??RCC_LSEConfig_0
\ 0000000E 0428 CMP R0,#+4
\ 00000010 02D0 BEQ.N ??RCC_LSEConfig_1
\ 00000012 00BD POP {PC}
596 {
597 case RCC_LSE_ON:
598 /* Set LSEON bit */
599 *(vu8 *) BDCR_BASE = RCC_LSE_ON;
\ ??RCC_LSEConfig_0:
\ 00000014 0870 STRB R0,[R1, #+0]
\ 00000016 00BD POP {PC}
600 break;
601
602 case RCC_LSE_Bypass:
603 /* Set LSEBYP and LSEON bits */
604 *(vu8 *) BDCR_BASE = RCC_LSE_Bypass | RCC_LSE_ON;
\ ??RCC_LSEConfig_1:
\ 00000018 0520 MOVS R0,#+5
\ 0000001A 0870 STRB R0,[R1, #+0]
605 break;
606
607 default:
608 break;
609 }
610 }
\ 0000001C 00BD POP {PC} ;; return
611
612 /*******************************************************************************
613 * Function Name : RCC_LSICmd
614 * Description : Enables or disables the Internal Low Speed oscillator (LSI).
615 * LSI can not be disabled if the IWDG is running.
616 * Input : - NewState: new state of the LSI.
617 * This parameter can be: ENABLE or DISABLE.
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