📄 stm32f10x_rcc.lst
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279
280 /*******************************************************************************
281 * Function Name : RCC_PLLConfig
282 * Description : Configures the PLL clock source and multiplication factor.
283 * This function must be used only when the PLL is disabled.
284 * Input : - RCC_PLLSource: specifies the PLL entry clock source.
285 * This parameter can be one of the following values:
286 * - RCC_PLLSource_HSI_Div2: HSI oscillator clock divided
287 * by 2 selected as PLL clock entry
288 * - RCC_PLLSource_HSE_Div1: HSE oscillator clock selected
289 * as PLL clock entry
290 * - RCC_PLLSource_HSE_Div2: HSE oscillator clock divided
291 * by 2 selected as PLL clock entry
292 * - RCC_PLLMul: specifies the PLL multiplication factor.
293 * This parameter can be RCC_PLLMul_x where x:[2,16]
294 * Output : None
295 * Return : None
296 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
297 void RCC_PLLConfig(u32 RCC_PLLSource, u32 RCC_PLLMul)
298 {
\ RCC_PLLConfig:
\ 00000000 10B5 PUSH {R4,LR}
299 u32 tmpreg = 0;
300
301 /* Check the parameters */
302 assert(IS_RCC_PLL_SOURCE(RCC_PLLSource));
303 assert(IS_RCC_PLL_MUL(RCC_PLLMul));
304
305 tmpreg = RCC->CFGR;
\ 00000002 .... LDR.N R2,??DataTable14 ;; 0x40021004
\ 00000004 1368 LDR R3,[R2, #+0]
306
307 /* Clear PLLSRC, PLLXTPRE and PLLMUL[21:18] bits */
308 tmpreg &= CFGR_PLL_Mask;
309
310 /* Set the PLL configuration bits */
311 tmpreg |= RCC_PLLSource | RCC_PLLMul;
312
313 /* Store the new value */
314 RCC->CFGR = tmpreg;
\ 00000006 7FF47C14 MVNS R4,#+4128768
\ 0000000A 1C40 ANDS R4,R4,R3
\ 0000000C 2043 ORRS R0,R0,R4
\ 0000000E 0143 ORRS R1,R1,R0
\ 00000010 1160 STR R1,[R2, #+0]
315 }
\ 00000012 10BD POP {R4,PC} ;; return
316
317 /*******************************************************************************
318 * Function Name : RCC_PLLCmd
319 * Description : Enables or disables the PLL.
320 * The PLL can not be disabled if it is used as system clock.
321 * Input : - NewState: new state of the PLL.
322 * This parameter can be: ENABLE or DISABLE.
323 * Output : None
324 * Return : None
325 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
326 void RCC_PLLCmd(FunctionalState NewState)
327 {
328 /* Check the parameters */
329 assert(IS_FUNCTIONAL_STATE(NewState));
330
331 *(vu32 *) CR_PLLON_BB = (u32)NewState;
\ RCC_PLLCmd:
\ 00000000 0149 LDR.N R1,??RCC_PLLCmd_0 ;; 0x42420060
\ 00000002 0860 STR R0,[R1, #+0]
332 }
\ 00000004 7047 BX LR ;; return
\ 00000006 00BF Nop
\ ??RCC_PLLCmd_0:
\ 00000008 60004242 DC32 0x42420060
333
334 /*******************************************************************************
335 * Function Name : RCC_SYSCLKConfig
336 * Description : Configures the system clock (SYSCLK).
337 * Input : - RCC_SYSCLKSource: specifies the clock source used as system
338 * clock. This parameter can be one of the following values:
339 * - RCC_SYSCLKSource_HSI: HSI selected as system clock
340 * - RCC_SYSCLKSource_HSE: HSE selected as system clock
341 * - RCC_SYSCLKSource_PLLCLK: PLL selected as system clock
342 * Output : None
343 * Return : None
344 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
345 void RCC_SYSCLKConfig(u32 RCC_SYSCLKSource)
346 {
347 u32 tmpreg = 0;
348
349 /* Check the parameters */
350 assert(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
351
352 tmpreg = RCC->CFGR;
\ RCC_SYSCLKConfig:
\ 00000000 .... LDR.N R1,??DataTable14 ;; 0x40021004
\ 00000002 0A68 LDR R2,[R1, #+0]
353
354 /* Clear SW[1:0] bits */
355 tmpreg &= CFGR_SW_Mask;
356
357 /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
358 tmpreg |= RCC_SYSCLKSource;
359
360 /* Store the new value */
361 RCC->CFGR = tmpreg;
\ 00000004 0323 MOVS R3,#+3
\ 00000006 9A43 BICS R2,R2,R3
\ 00000008 1043 ORRS R0,R0,R2
\ 0000000A 0860 STR R0,[R1, #+0]
362 }
\ 0000000C 7047 BX LR ;; return
363
364 /*******************************************************************************
365 * Function Name : RCC_GetSYSCLKSource
366 * Description : Returns the clock source used as system clock.
367 * Input : None
368 * Output : None
369 * Return : The clock source used as system clock. The returned value can
370 * be one of the following:
371 * - 0x00: HSI used as system clock
372 * - 0x04: HSE used as system clock
373 * - 0x08: PLL used as system clock
374 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
375 u8 RCC_GetSYSCLKSource(void)
376 {
377 return ((u8)(RCC->CFGR & CFGR_SWS_Mask));
\ RCC_GetSYSCLKSource:
\ 00000000 .... LDR.N R0,??DataTable14 ;; 0x40021004
\ 00000002 0068 LDR R0,[R0, #+0]
\ 00000004 10F00C00 ANDS R0,R0,#0xC
\ 00000008 7047 BX LR ;; return
378 }
379
380 /*******************************************************************************
381 * Function Name : RCC_HCLKConfig
382 * Description : Configures the AHB clock (HCLK).
383 * Input : - RCC_HCLK: defines the AHB clock. This clock is derived
384 * from the system clock (SYSCLK).
385 * This parameter can be one of the following values:
386 * - RCC_SYSCLK_Div1: AHB clock = SYSCLK
387 * - RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
388 * - RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
389 * - RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
390 * - RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
391 * - RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
392 * - RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
393 * - RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
394 * - RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
395 * Output : None
396 * Return : None
397 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
398 void RCC_HCLKConfig(u32 RCC_HCLK)
399 {
400 u32 tmpreg = 0;
401
402 /* Check the parameters */
403 assert(IS_RCC_HCLK(RCC_HCLK));
404
405 tmpreg = RCC->CFGR;
\ RCC_HCLKConfig:
\ 00000000 .... LDR.N R1,??DataTable14 ;; 0x40021004
\ 00000002 0A68 LDR R2,[R1, #+0]
406
407 /* Clear HPRE[7:4] bits */
408 tmpreg &= CFGR_HPRE_Reset_Mask;
409
410 /* Set HPRE[7:4] bits according to RCC_HCLK value */
411 tmpreg |= RCC_HCLK;
412
413 /* Store the new value */
414 RCC->CFGR = tmpreg;
\ 00000004 F023 MOVS R3,#+240
\ 00000006 9A43 BICS R2,R2,R3
\ 00000008 1043 ORRS R0,R0,R2
\ 0000000A 0860 STR R0,[R1, #+0]
415 }
\ 0000000C 7047 BX LR ;; return
416
417 /*******************************************************************************
418 * Function Name : RCC_PCLK1Config
419 * Description : Configures the Low Speed APB clock (PCLK1).
420 * Input : - RCC_PCLK1: defines the APB1 clock. This clock is derived
421 * from the AHB clock (HCLK).
422 * This parameter can be one of the following values:
423 * - RCC_HCLK_Div1: APB1 clock = HCLK
424 * - RCC_HCLK_Div2: APB1 clock = HCLK/2
425 * - RCC_HCLK_Div4: APB1 clock = HCLK/4
426 * - RCC_HCLK_Div8: APB1 clock = HCLK/8
427 * - RCC_HCLK_Div16: APB1 clock = HCLK/16
428 * Output : None
429 * Return : None
430 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
431 void RCC_PCLK1Config(u32 RCC_PCLK1)
432 {
433 u32 tmpreg = 0;
434
435 /* Check the parameters */
436 assert(IS_RCC_PCLK(RCC_PCLK1));
437
438 tmpreg = RCC->CFGR;
\ RCC_PCLK1Config:
\ 00000000 .... LDR.N R1,??DataTable14 ;; 0x40021004
\ 00000002 0A68 LDR R2,[R1, #+0]
439
440 /* Clear PPRE1[10:8] bits */
441 tmpreg &= CFGR_PPRE1_Reset_Mask;
442
443 /* Set PPRE1[10:8] bits according to RCC_PCLK1 value */
444 tmpreg |= RCC_PCLK1;
445
446 /* Store the new value */
447 RCC->CFGR = tmpreg;
\ 00000004 7FF4E063 MVNS R3,#+1792
\ 00000008 1340 ANDS R3,R3,R2
\ 0000000A 1843 ORRS R0,R0,R3
\ 0000000C 0860 STR R0,[R1, #+0]
448 }
\ 0000000E 7047 BX LR ;; return
449
450 /*******************************************************************************
451 * Function Name : RCC_PCLK2Config
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