📄 stm32f10x_tim1.lst
字号:
\ 0000001E 0A60 STR R2,[R1, #+0]
485
486 /* Set the Output Polarity */
487 *(vu32 *) CCER_CC3P_BB = TIM1_OCInitStruct->TIM1_OCPolarity;
\ 00000020 091F SUBS R1,R1,#+4
\ 00000022 0289 LDRH R2,[R0, #+8]
\ 00000024 0A60 STR R2,[R1, #+0]
488
489 /* Set the Output N Polarity */
490 *(vu32 *) CCER_CC3NP_BB = TIM1_OCInitStruct->TIM1_OCNPolarity;
\ 00000026 0831 ADDS R1,R1,#+8
\ 00000028 4289 LDRH R2,[R0, #+10]
\ 0000002A 0A60 STR R2,[R1, #+0]
491
492 /* Set the Output Idle state */
493 *(vu32 *) CR2_OIS3_BB = TIM1_OCInitStruct->TIM1_OCIdleState;
\ 0000002C 0449 LDR.N R1,??TIM1_OC3Init_0 ;; 0x422580b0
\ 0000002E 8289 LDRH R2,[R0, #+12]
\ 00000030 0A60 STR R2,[R1, #+0]
494
495 /* Set the Output N Idle state */
496 *(vu32 *) CR2_OIS3N_BB = TIM1_OCInitStruct->TIM1_OCNIdleState;
\ 00000032 091D ADDS R1,R1,#+4
\ 00000034 C289 LDRH R2,[R0, #+14]
\ 00000036 0A60 STR R2,[R1, #+0]
497
498 /* Set the Pulse value */
499 TIM1->CCR3 = TIM1_OCInitStruct->TIM1_Pulse;
\ 00000038 .... LDR.N R1,??DataTable11 ;; 0x40012c3c
\ 0000003A C088 LDRH R0,[R0, #+6]
\ 0000003C 0880 STRH R0,[R1, #+0]
500 }
\ 0000003E 10BD POP {R4,PC} ;; return
\ ??TIM1_OC3Init_0:
\ 00000040 B0802542 DC32 0x422580b0
501
502 /*******************************************************************************
503 * Function Name : TIM1_OC4Init
504 * Description : Initializes the TIM1 Channel4 according to the specified
505 * parameters in the TIM1_OCInitStruct.
506 * Input : - TIM1_OCInitStruct: pointer to a TIM1_OCInitTypeDef structure that
507 * contains the configuration information for the TIM1 peripheral.
508 * Output : None
509 * Return : None
510 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
511 void TIM1_OC4Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct)
512 {
\ TIM1_OC4Init:
\ 00000000 10B5 PUSH {R4,LR}
513 u32 tmpccmr = 0;
514
515 /* Check the parameters */
516 assert(IS_TIM1_OC_MODE(TIM1_OCInitStruct->TIM1_OCMode));
517 assert(IS_TIM1_OUTPUT_STATE(TIM1_OCInitStruct->TIM1_OutputState));
518 assert(IS_TIM1_OC_POLARITY(TIM1_OCInitStruct->TIM1_OCPolarity));
519 assert(IS_TIM1_OCIDLE_STATE(TIM1_OCInitStruct->TIM1_OCIdleState));
520
521 tmpccmr = TIM1->CCMR2;
\ 00000002 .... LDR.N R2,??DataTable12 ;; 0x40012c1c
\ 00000004 1388 LDRH R3,[R2, #+0]
522
523 /* Disable the Channel 4: Reset the CCE Bit */
524 *(vu32 *) CCER_CC4E_BB = CCER_CCE_Reset;
\ 00000006 .... LDR.N R1,??DataTable13 ;; 0x42258430
\ 00000008 0024 MOVS R4,#+0
\ 0000000A 0C60 STR R4,[R1, #+0]
525
526 /* Reset the Output Compare Bits */
527 tmpccmr &= OC24Mode_Mask;
528
529 /* Set the Ouput Compare Mode */
530 tmpccmr |= (u32)TIM1_OCInitStruct->TIM1_OCMode << 8;
531
532 TIM1->CCMR2 = (u16)tmpccmr;
\ 0000000C DBB2 UXTB R3,R3
\ 0000000E 0488 LDRH R4,[R0, #+0]
\ 00000010 53EA0423 ORRS R3,R3,R4, LSL #+8
\ 00000014 1380 STRH R3,[R2, #+0]
533
534 /* Set the Output State */
535 *(vu32 *) CCER_CC4E_BB = TIM1_OCInitStruct->TIM1_OutputState;
\ 00000016 4288 LDRH R2,[R0, #+2]
\ 00000018 0A60 STR R2,[R1, #+0]
536
537 /* Set the Output Polarity */
538 *(vu32 *) CCER_CC4P_BB = TIM1_OCInitStruct->TIM1_OCPolarity;
\ 0000001A 091D ADDS R1,R1,#+4
\ 0000001C 0289 LDRH R2,[R0, #+8]
\ 0000001E 0A60 STR R2,[R1, #+0]
539
540 /* Set the Output Idle state */
541 *(vu32 *) CR2_OIS4_BB = TIM1_OCInitStruct->TIM1_OCIdleState;
\ 00000020 0349 LDR.N R1,??TIM1_OC4Init_0 ;; 0x422580b8
\ 00000022 8289 LDRH R2,[R0, #+12]
\ 00000024 0A60 STR R2,[R1, #+0]
542
543 /* Set the Pulse value */
544 TIM1->CCR4 = TIM1_OCInitStruct->TIM1_Pulse;
\ 00000026 .... LDR.N R1,??DataTable14 ;; 0x40012c40
\ 00000028 C088 LDRH R0,[R0, #+6]
\ 0000002A 0880 STRH R0,[R1, #+0]
545 }
\ 0000002C 10BD POP {R4,PC} ;; return
\ 0000002E 00BF Nop
\ ??TIM1_OC4Init_0:
\ 00000030 B8802542 DC32 0x422580b8
546
547 /*******************************************************************************
548 * Function Name : TIM1_BDTRConfig
549 * Description : Configures the: Break feature, dead time, Lock level, the OSSI,
550 * the OSSR State and the AOE(automatic output enable).
551 * Input : - TIM1_BDTRInitStruct: pointer to a TIM1_BDTRInitTypeDef
552 * structure that contains the BDTR Register configuration
553 * information for the TIM1 peripheral.
554 * Output : None
555 * Return : None
556 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
557 void TIM1_BDTRConfig(TIM1_BDTRInitTypeDef *TIM1_BDTRInitStruct)
558 {
559 u16 tmpbdtr = 0;
560
561 /* Check the parameters */
562 assert(IS_TIM1_OSSR_STATE(TIM1_BDTRInitStruct->TIM1_OSSRState));
563 assert(IS_TIM1_OSSI_STATE(TIM1_BDTRInitStruct->TIM1_OSSIState));
564 assert(IS_TIM1_LOCK_LEVEL(TIM1_BDTRInitStruct->TIM1_LOCKLevel));
565 assert(IS_TIM1_BREAK_STATE(TIM1_BDTRInitStruct->TIM1_Break));
566 assert(IS_TIM1_BREAK_POLARITY(TIM1_BDTRInitStruct->TIM1_BreakPolarity));
567 assert(IS_TIM1_AUTOMATIC_OUTPUT_STATE(TIM1_BDTRInitStruct->TIM1_AutomaticOutput));
568
569 tmpbdtr = TIM1->BDTR;
\ TIM1_BDTRConfig:
\ 00000000 0849 LDR.N R1,??TIM1_BDTRConfig_0 ;; 0x40012c44
\ 00000002 0A88 LDRH R2,[R1, #+0]
570
571 /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State,
572 the OSSI State, the dead time value and the Automatic Output Enable Bit */
573
574 tmpbdtr = (u32)TIM1_BDTRInitStruct->TIM1_OSSRState | TIM1_BDTRInitStruct->TIM1_OSSIState |
575 TIM1_BDTRInitStruct->TIM1_LOCKLevel | TIM1_BDTRInitStruct->TIM1_DeadTime |
576 TIM1_BDTRInitStruct->TIM1_Break | TIM1_BDTRInitStruct->TIM1_BreakPolarity |
577 TIM1_BDTRInitStruct->TIM1_AutomaticOutput;
578
579 TIM1->BDTR = tmpbdtr;
\ 00000004 0288 LDRH R2,[R0, #+0]
\ 00000006 4388 LDRH R3,[R0, #+2]
\ 00000008 1343 ORRS R3,R3,R2
\ 0000000A 8288 LDRH R2,[R0, #+4]
\ 0000000C 1A43 ORRS R2,R2,R3
\ 0000000E C388 LDRH R3,[R0, #+6]
\ 00000010 1343 ORRS R3,R3,R2
\ 00000012 0289 LDRH R2,[R0, #+8]
\ 00000014 1A43 ORRS R2,R2,R3
\ 00000016 4389 LDRH R3,[R0, #+10]
\ 00000018 1343 ORRS R3,R3,R2
\ 0000001A 8089 LDRH R0,[R0, #+12]
\ 0000001C 1843 ORRS R0,R0,R3
\ 0000001E 0880 STRH R0,[R1, #+0]
580 }
\ 00000020 7047 BX LR ;; return
\ 00000022 00BF Nop
\ ??TIM1_BDTRConfig_0:
\ 00000024 442C0140 DC32 0x40012c44
581
582 /*******************************************************************************
583 * Function Name : TIM1_ICInit
584 * Description : Initializes the TIM1 peripheral according to the specified
585 * parameters in the TIM1_ICInitStruct.
586 * Input : - TIM1_ICInitStruct: pointer to a TIM1_ICInitTypeDef structure
587 * that contains the configuration information for the specified
588 * TIM1 peripheral.
589 * Output : None
590 * Return : None
591 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
592 void TIM1_ICInit(TIM1_ICInitTypeDef* TIM1_ICInitStruct)
593 {
\ TIM1_ICInit:
\ 00000000 10B5 PUSH {R4,LR}
\ 00000002 0400 MOVS R4,R0
594 /* Check the parameters */
595 assert(IS_TIM1_CHANNEL(TIM1_ICInitStruct->TIM1_Channel));
596 assert(IS_TIM1_IC_POLARITY(TIM1_ICInitStruct->TIM1_ICPolarity));
597 assert(IS_TIM1_IC_SELECTION(TIM1_ICInitStruct->TIM1_ICSelection));
598 assert(IS_TIM1_IC_PRESCALER(TIM1_ICInitStruct->TIM1_ICPrescaler));
599 assert(IS_TIM1_IC_FILTER(TIM1_ICInitStruct->TIM1_ICFilter));
600
601 if (TIM1_ICInitStruct->TIM1_Channel == TIM1_Channel_1)
\ 00000004 2088 LDRH R0,[R4, #+0]
\ 00000006 0028 CMP R0,#+0
\ 00000008 08D1 BNE.N ??TIM1_ICInit_0
602 {
603 /* TI1 Configuration */
604 TI1_Config(TIM1_ICInitStruct->TIM1_ICPolarity,
605 TIM1_ICInitStruct->TIM1_ICSelection,
606 TIM1_ICInitStruct->TIM1_ICFilter);
\ 0000000A 227A LDRB R2,[R4, #+8]
\ 0000000C A188 LDRH R1,[R4, #+4]
\ 0000000E 6088 LDRH R0,[R4, #+2]
\ 00000010 ........ BL TI1_Config
607
608 /* Set the Input Capture Prescaler value */
609 TIM1_SetIC1Prescaler(TIM1_ICInitStruct->TIM1_ICPrescaler);
\ 00000014 E088 LDRH R0,[R4, #+6]
\ 00000016 ........ BL TIM1_SetIC1Prescaler
\ 0000001A 10BD POP {R4,PC}
610 }
611 else if (TIM1_ICInitStruct->TIM1_Channel == TIM1_Channel_2)
\ ??TIM1_ICInit_0:
\ 0000001C 0128 CMP R0,#+1
\ 0000001E 08D1 BNE.N ??TIM1_ICInit_1
612 {
613 /* TI2 Configuration */
614 TI2_Config(TIM1_ICInitStruct->TIM1_ICPolarity,
615 TIM1_ICInitStruct->TIM1_ICSelection,
616 TIM1_ICInitStruct->TIM1_ICFilter);
\ 00000020 227A LDRB R2,[R4, #+8]
\ 00000022 A188 LDRH R1,[R4, #+4]
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -