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📄 stm32f10x_tim1.lst

📁 针对STM32F103的UCOS移植
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    348            assert(IS_TIM1_OC_POLARITY(TIM1_OCInitStruct->TIM1_OCPolarity));
    349            assert(IS_TIM1_OCN_POLARITY(TIM1_OCInitStruct->TIM1_OCNPolarity));
    350            assert(IS_TIM1_OCIDLE_STATE(TIM1_OCInitStruct->TIM1_OCIdleState));
    351            assert(IS_TIM1_OCNIDLE_STATE(TIM1_OCInitStruct->TIM1_OCNIdleState)); 
    352          
    353            tmpccmr = TIM1->CCMR1;
   \   00000002   ....               LDR.N    R1,??DataTable5  ;; 0x40012c18
   \   00000004   0A88               LDRH     R2,[R1, #+0]
    354          
    355            /* Disable the Channel 1: Reset the CCE Bit */
    356            *(vu32 *) CCER_CC1E_BB = CCER_CCE_Reset;
   \   00000006   ....               LDR.N    R3,??DataTable2  ;; 0x42258400
   \   00000008   0024               MOVS     R4,#+0
   \   0000000A   1C60               STR      R4,[R3, #+0]
    357          
    358            /* Reset the Output Compare Bits */
    359             tmpccmr &= OC13Mode_Mask;
    360          
    361            /* Set the Ouput Compare Mode */
    362            tmpccmr |= TIM1_OCInitStruct->TIM1_OCMode;
    363          
    364            TIM1->CCMR1 = tmpccmr;
   \   0000000C   12F47F42           ANDS     R2,R2,#0xFF00
   \   00000010   0488               LDRH     R4,[R0, #+0]
   \   00000012   1443               ORRS     R4,R4,R2
   \   00000014   0C80               STRH     R4,[R1, #+0]
    365          
    366            /* Set the Output State */
    367            *(vu32 *) CCER_CC1E_BB = TIM1_OCInitStruct->TIM1_OutputState;
   \   00000016   4188               LDRH     R1,[R0, #+2]
   \   00000018   1960               STR      R1,[R3, #+0]
    368          
    369            /* Set the Output N State */
    370            *(vu32 *) CCER_CC1NE_BB = TIM1_OCInitStruct->TIM1_OutputNState;
   \   0000001A   ....               LDR.N    R1,??DataTable3  ;; 0x42258408
   \   0000001C   8288               LDRH     R2,[R0, #+4]
   \   0000001E   0A60               STR      R2,[R1, #+0]
    371          
    372            /* Set the Output Polarity */
    373            *(vu32 *) CCER_CC1P_BB = TIM1_OCInitStruct->TIM1_OCPolarity;
   \   00000020   091F               SUBS     R1,R1,#+4
   \   00000022   0289               LDRH     R2,[R0, #+8]
   \   00000024   0A60               STR      R2,[R1, #+0]
    374          
    375            /* Set the Output N Polarity */
    376            *(vu32 *) CCER_CC1NP_BB = TIM1_OCInitStruct->TIM1_OCNPolarity;
   \   00000026   0831               ADDS     R1,R1,#+8
   \   00000028   4289               LDRH     R2,[R0, #+10]
   \   0000002A   0A60               STR      R2,[R1, #+0]
    377          
    378            /* Set the Output Idle state */
    379            *(vu32 *) CR2_OIS1_BB = TIM1_OCInitStruct->TIM1_OCIdleState;
   \   0000002C   0449               LDR.N    R1,??TIM1_OC1Init_0  ;; 0x422580a0
   \   0000002E   8289               LDRH     R2,[R0, #+12]
   \   00000030   0A60               STR      R2,[R1, #+0]
    380          
    381            /* Set the Output N Idle state */
    382            *(vu32 *) CR2_OIS1N_BB = TIM1_OCInitStruct->TIM1_OCNIdleState;
   \   00000032   091D               ADDS     R1,R1,#+4
   \   00000034   C289               LDRH     R2,[R0, #+14]
   \   00000036   0A60               STR      R2,[R1, #+0]
    383          
    384            /* Set the Pulse value */
    385            TIM1->CCR1 = TIM1_OCInitStruct->TIM1_Pulse;
   \   00000038   ....               LDR.N    R1,??DataTable4  ;; 0x40012c34
   \   0000003A   C088               LDRH     R0,[R0, #+6]
   \   0000003C   0880               STRH     R0,[R1, #+0]
    386          }
   \   0000003E   10BD               POP      {R4,PC}          ;; return
   \                     ??TIM1_OC1Init_0:
   \   00000040   A0802542           DC32     0x422580a0
    387          
    388          /*******************************************************************************
    389          * Function Name  : TIM1_OC2Init
    390          * Description    : Initializes the TIM1 Channel2 according to the specified
    391          *                  parameters in the TIM1_OCInitStruct.
    392          * Input          : - TIM1_OCInitStruct: pointer to a TIM1_OCInitTypeDef structure that
    393          *                    contains the configuration information for the TIM1 peripheral.
    394          * Output         : None
    395          * Return         : None
    396          *******************************************************************************/

   \                                 In segment CODE, align 4, keep-with-next
    397          void TIM1_OC2Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct)
    398          {
   \                     TIM1_OC2Init:
   \   00000000   10B5               PUSH     {R4,LR}
    399            u32 tmpccmr = 0;
    400          
    401            /* Check the parameters */
    402            assert(IS_TIM1_OC_MODE(TIM1_OCInitStruct->TIM1_OCMode));
    403            assert(IS_TIM1_OUTPUT_STATE(TIM1_OCInitStruct->TIM1_OutputState));
    404            assert(IS_TIM1_OUTPUTN_STATE(TIM1_OCInitStruct->TIM1_OutputNState));
    405            assert(IS_TIM1_OC_POLARITY(TIM1_OCInitStruct->TIM1_OCPolarity));
    406            assert(IS_TIM1_OCN_POLARITY(TIM1_OCInitStruct->TIM1_OCNPolarity));
    407            assert(IS_TIM1_OCIDLE_STATE(TIM1_OCInitStruct->TIM1_OCIdleState));
    408            assert(IS_TIM1_OCNIDLE_STATE(TIM1_OCInitStruct->TIM1_OCNIdleState));
    409          
    410            tmpccmr = TIM1->CCMR1;
   \   00000002   ....               LDR.N    R2,??DataTable5  ;; 0x40012c18
   \   00000004   1388               LDRH     R3,[R2, #+0]
    411          
    412            /* Disable the Channel 2: Reset the CCE Bit */
    413            *(vu32 *) CCER_CC2E_BB = CCER_CCE_Reset;
   \   00000006   ....               LDR.N    R1,??DataTable6  ;; 0x42258410
   \   00000008   0024               MOVS     R4,#+0
   \   0000000A   0C60               STR      R4,[R1, #+0]
    414          
    415            /* Reset the Output Compare Bits */
    416             tmpccmr &= OC24Mode_Mask;
    417          
    418            /* Set the Ouput Compare Mode */
    419            tmpccmr |= (u32)TIM1_OCInitStruct->TIM1_OCMode << 8;
    420          
    421            TIM1->CCMR1 = (u16)tmpccmr;
   \   0000000C   DBB2               UXTB     R3,R3
   \   0000000E   0488               LDRH     R4,[R0, #+0]
   \   00000010   53EA0423           ORRS     R3,R3,R4, LSL #+8
   \   00000014   1380               STRH     R3,[R2, #+0]
    422          
    423            /* Set the Output State */
    424            *(vu32 *) CCER_CC2E_BB = TIM1_OCInitStruct->TIM1_OutputState;
   \   00000016   4288               LDRH     R2,[R0, #+2]
   \   00000018   0A60               STR      R2,[R1, #+0]
    425          
    426            /* Set the Output N State */
    427            *(vu32 *) CCER_CC2NE_BB = TIM1_OCInitStruct->TIM1_OutputNState;
   \   0000001A   0831               ADDS     R1,R1,#+8
   \   0000001C   8288               LDRH     R2,[R0, #+4]
   \   0000001E   0A60               STR      R2,[R1, #+0]
    428          
    429            /* Set the Output Polarity */
    430            *(vu32 *) CCER_CC2P_BB = TIM1_OCInitStruct->TIM1_OCPolarity;
   \   00000020   091F               SUBS     R1,R1,#+4
   \   00000022   0289               LDRH     R2,[R0, #+8]
   \   00000024   0A60               STR      R2,[R1, #+0]
    431          
    432            /* Set the Output N Polarity */
    433            *(vu32 *) CCER_CC2NP_BB = TIM1_OCInitStruct->TIM1_OCNPolarity;
   \   00000026   0831               ADDS     R1,R1,#+8
   \   00000028   4289               LDRH     R2,[R0, #+10]
   \   0000002A   0A60               STR      R2,[R1, #+0]
    434          
    435            /* Set the Output Idle state */
    436            *(vu32 *) CR2_OIS2_BB = TIM1_OCInitStruct->TIM1_OCIdleState;
   \   0000002C   0449               LDR.N    R1,??TIM1_OC2Init_0  ;; 0x422580a8
   \   0000002E   8289               LDRH     R2,[R0, #+12]
   \   00000030   0A60               STR      R2,[R1, #+0]
    437          
    438            /* Set the Output N Idle state */
    439            *(vu32 *) CR2_OIS2N_BB = TIM1_OCInitStruct->TIM1_OCNIdleState;
   \   00000032   091D               ADDS     R1,R1,#+4
   \   00000034   C289               LDRH     R2,[R0, #+14]
   \   00000036   0A60               STR      R2,[R1, #+0]
    440          
    441            /* Set the Pulse value */
    442            TIM1->CCR2 = TIM1_OCInitStruct->TIM1_Pulse;
   \   00000038   ....               LDR.N    R1,??DataTable7  ;; 0x40012c38
   \   0000003A   C088               LDRH     R0,[R0, #+6]
   \   0000003C   0880               STRH     R0,[R1, #+0]
    443          }
   \   0000003E   10BD               POP      {R4,PC}          ;; return
   \                     ??TIM1_OC2Init_0:
   \   00000040   A8802542           DC32     0x422580a8
    444          
    445          /*******************************************************************************
    446          * Function Name  : TIM1_OC3Init
    447          * Description    : Initializes the TIM1 Channel3 according to the specified
    448          *                  parameters in the TIM1_OCInitStruct.
    449          * Input          : - TIM1_OCInitStruct: pointer to a TIM1_OCInitTypeDef structure that
    450          *                    contains the configuration information for the TIM1 peripheral.
    451          * Output         : None
    452          * Return         : None
    453          *******************************************************************************/

   \                                 In segment CODE, align 4, keep-with-next
    454          void TIM1_OC3Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct)
    455          {
   \                     TIM1_OC3Init:
   \   00000000   10B5               PUSH     {R4,LR}
    456            u16 tmpccmr = 0;
    457          
    458            /* Check the parameters */
    459            assert(IS_TIM1_OC_MODE(TIM1_OCInitStruct->TIM1_OCMode));
    460            assert(IS_TIM1_OUTPUT_STATE(TIM1_OCInitStruct->TIM1_OutputState));
    461            assert(IS_TIM1_OUTPUTN_STATE(TIM1_OCInitStruct->TIM1_OutputNState));
    462            assert(IS_TIM1_OC_POLARITY(TIM1_OCInitStruct->TIM1_OCPolarity));
    463            assert(IS_TIM1_OCN_POLARITY(TIM1_OCInitStruct->TIM1_OCNPolarity));
    464            assert(IS_TIM1_OCIDLE_STATE(TIM1_OCInitStruct->TIM1_OCIdleState));
    465            assert(IS_TIM1_OCNIDLE_STATE(TIM1_OCInitStruct->TIM1_OCNIdleState));
    466          
    467            tmpccmr = TIM1->CCMR2;
   \   00000002   ....               LDR.N    R1,??DataTable12  ;; 0x40012c1c
   \   00000004   0A88               LDRH     R2,[R1, #+0]
    468          
    469            /* Disable the Channel 3: Reset the CCE Bit */
    470            *(vu32 *) CCER_CC3E_BB = CCER_CCE_Reset;
   \   00000006   ....               LDR.N    R3,??DataTable9  ;; 0x42258420
   \   00000008   0024               MOVS     R4,#+0
   \   0000000A   1C60               STR      R4,[R3, #+0]
    471          
    472            /* Reset the Output Compare Bits */
    473             tmpccmr &= OC13Mode_Mask;
    474          
    475            /* Set the Ouput Compare Mode */
    476            tmpccmr |= TIM1_OCInitStruct->TIM1_OCMode;
    477          
    478            TIM1->CCMR2 = tmpccmr;
   \   0000000C   12F47F42           ANDS     R2,R2,#0xFF00
   \   00000010   0488               LDRH     R4,[R0, #+0]
   \   00000012   1443               ORRS     R4,R4,R2
   \   00000014   0C80               STRH     R4,[R1, #+0]
    479          
    480            /* Set the Output State */
    481            *(vu32 *) CCER_CC3E_BB = TIM1_OCInitStruct->TIM1_OutputState;
   \   00000016   4188               LDRH     R1,[R0, #+2]
   \   00000018   1960               STR      R1,[R3, #+0]
    482          
    483            /* Set the Output N State */
    484            *(vu32 *) CCER_CC3NE_BB = TIM1_OCInitStruct->TIM1_OutputNState;
   \   0000001A   ....               LDR.N    R1,??DataTable10  ;; 0x42258428
   \   0000001C   8288               LDRH     R2,[R0, #+4]

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