📄 stm32f10x_tim.lst
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\ 0000002A 0121 MOVS R1,#+1
\ 0000002C 0220 MOVS R0,#+2
\ 0000002E ........ _BLF RCC_APB1PeriphResetCmd,??RCC_APB1PeriphResetCmd??rT
135 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
\ 00000032 0021 MOVS R1,#+0
\ 00000034 0220 MOVS R0,#+2
\ 00000036 ........ _BLF RCC_APB1PeriphResetCmd,??RCC_APB1PeriphResetCmd??rT
\ 0000003A 00BD POP {PC}
136 break;
137
138 case TIM4_BASE:
139 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);
\ ??TIM_DeInit_3:
\ 0000003C 0121 MOVS R1,#+1
\ 0000003E 0420 MOVS R0,#+4
\ 00000040 ........ _BLF RCC_APB1PeriphResetCmd,??RCC_APB1PeriphResetCmd??rT
140 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);
\ 00000044 0021 MOVS R1,#+0
\ 00000046 0420 MOVS R0,#+4
\ 00000048 ........ _BLF RCC_APB1PeriphResetCmd,??RCC_APB1PeriphResetCmd??rT
141 break;
142
143 default:
144 break;
145 }
146 }
\ 0000004C 00BD POP {PC} ;; return
\ 0000004E 00BF Nop
\ ??TIM_DeInit_1:
\ 00000050 00040040 DC32 0x40000400
\ 00000054 00080040 DC32 0x40000800
147
148 /*******************************************************************************
149 * Function Name : TIM_TimeBaseInit
150 * Description : Initializes the TIMx Time Base Unit peripheral according to
151 * the specified parameters in the TIM_TimeBaseInitStruct.
152 * Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
153 * - TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef
154 * structure that contains the configuration information for
155 * the specified TIM peripheral.
156 * Output : None
157 * Return : None
158 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
159 void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
160 {
161 /* Check the parameters */
162 assert(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));
163 assert(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));
164
165 /* Set the Autoreload value */
166 TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;
\ TIM_TimeBaseInit:
\ 00000000 0A88 LDRH R2,[R1, #+0]
\ 00000002 8285 STRH R2,[R0, #+44]
167
168 /* Set the Prescaler value */
169 TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
\ 00000004 4A88 LDRH R2,[R1, #+2]
\ 00000006 0285 STRH R2,[R0, #+40]
170
171 /* Select the Counter Mode and set the clock division */
172 TIMx->CR1 &= CR1_CKD_Mask & CR1_CounterMode_Mask;
\ 00000008 0288 LDRH R2,[R0, #+0]
\ 0000000A 12F09F02 ANDS R2,R2,#0x9F
\ 0000000E 0280 STRH R2,[R0, #+0]
173 TIMx->CR1 |= (u32)TIM_TimeBaseInitStruct->TIM_ClockDivision |
174 TIM_TimeBaseInitStruct->TIM_CounterMode;
\ 00000010 0288 LDRH R2,[R0, #+0]
\ 00000012 8B88 LDRH R3,[R1, #+4]
\ 00000014 C988 LDRH R1,[R1, #+6]
\ 00000016 1943 ORRS R1,R1,R3
\ 00000018 1143 ORRS R1,R1,R2
\ 0000001A 0180 STRH R1,[R0, #+0]
175 }
\ 0000001C 7047 BX LR ;; return
176 /*******************************************************************************
177 * Function Name : TIM_OCInit
178 * Description : Initializes the TIMx peripheral according to the specified
179 * parameters in the TIM_OCInitStruct.
180 * Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
181 * - TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
182 * that contains the configuration information for the specified
183 * TIM peripheral.
184 * Output : None
185 * Return : None
186 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
187 void TIM_OCInit(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
188 {
\ TIM_OCInit:
\ 00000000 30B5 PUSH {R4,R5,LR}
189 u32 tmpccmrx = 0, tmpccer = 0;
190
191 /* Check the parameters */
192 assert(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
193 assert(IS_TIM_CHANNEL(TIM_OCInitStruct->TIM_Channel));
194 assert(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
195
196 tmpccer = TIMx->CCER;
\ 00000002 028C LDRH R2,[R0, #+32]
197
198 if ((TIM_OCInitStruct->TIM_Channel == (u16)TIM_Channel_1) ||
199 (TIM_OCInitStruct->TIM_Channel == (u16)TIM_Channel_2))
\ 00000004 2E4B LDR.N R3,??TIM_OCInit_0 ;; Tab_OCModeMask
\ 00000006 4C88 LDRH R4,[R1, #+2]
\ 00000008 002C CMP R4,#+0
\ 0000000A 01D0 BEQ.N ??TIM_OCInit_1
\ 0000000C 012C CMP R4,#+1
\ 0000000E 27D1 BNE.N ??TIM_OCInit_2
200 {
201 tmpccmrx = TIMx->CCMR1;
\ ??TIM_OCInit_1:
\ 00000010 058B LDRH R5,[R0, #+24]
202
203 /* Reset the Output Compare Bits */
204 tmpccmrx &= Tab_OCModeMask[TIM_OCInitStruct->TIM_Channel];
\ 00000012 33F81440 LDRH R4,[R3, R4, LSL #+1]
\ 00000016 2C40 ANDS R4,R4,R5
205
206 /* Set the Output Polarity level */
207 tmpccer &= Tab_PolarityMask[TIM_OCInitStruct->TIM_Channel];
\ 00000018 4D88 LDRH R5,[R1, #+2]
\ 0000001A 13EB4503 ADDS R3,R3,R5, LSL #+1
\ 0000001E 1B89 LDRH R3,[R3, #+8]
\ 00000020 1340 ANDS R3,R3,R2
208
209 if (TIM_OCInitStruct->TIM_Channel == TIM_Channel_1)
\ 00000022 2A46 MOV R2,R5
\ 00000024 002A CMP R2,#+0
\ 00000026 028C LDRH R2,[R0, #+32]
\ 00000028 0BD1 BNE.N ??TIM_OCInit_3
210 {
211 /* Disable the Channel 1: Reset the CCE Bit */
212 TIMx->CCER &= CCER_CC1E_Reset;
\ 0000002A .... LDR.N R5,??DataTable0 ;; 0xfffe
\ 0000002C 1540 ANDS R5,R5,R2
\ 0000002E 0584 STRH R5,[R0, #+32]
213
214 /* Select the Output Compare Mode */
215 tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
\ 00000030 0D88 LDRH R5,[R1, #+0]
\ 00000032 2543 ORRS R5,R5,R4
216
217 /* Set the Capture Compare Register value */
218 TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;
\ 00000034 8A88 LDRH R2,[R1, #+4]
\ 00000036 8286 STRH R2,[R0, #+52]
219
220 /* Set the Capture Compare Enable Bit */
221 tmpccer |= CCER_CC1E_Set;
222
223 /* Set the Capture Compare Polarity */
224 tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
\ 00000038 C988 LDRH R1,[R1, #+6]
\ 0000003A 51F00102 ORRS R2,R1,#0x1
\ 0000003E 1A43 ORRS R2,R2,R3
\ 00000040 0CE0 B.N ??TIM_OCInit_4
225 }
226 else /* TIM_Channel_2 */
227 {
228 /* Disable the Channel 2: Reset the CCE Bit */
229 TIMx->CCER &= CCER_CC2E_Reset;
\ ??TIM_OCInit_3:
\ 00000042 .... LDR.N R5,??DataTable1 ;; 0xffef
\ 00000044 1540 ANDS R5,R5,R2
\ 00000046 0584 STRH R5,[R0, #+32]
230
231 /* Select the Output Compare Mode */
232 tmpccmrx |= (u32)TIM_OCInitStruct->TIM_OCMode << 8;
\ 00000048 0A88 LDRH R2,[R1, #+0]
\ 0000004A 54EA0225 ORRS R5,R4,R2, LSL #+8
233
234 /* Set the Capture Compare Register value */
235 TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;
\ 0000004E 8A88 LDRH R2,[R1, #+4]
\ 00000050 0287 STRH R2,[R0, #+56]
236
237 /* Set the Capture Compare Enable Bit */
238 tmpccer |= CCER_CC2E_Set;
239
240 /* Set the Capture Compare Polarity */
241 tmpccer |= (u32)TIM_OCInitStruct->TIM_OCPolarity << 4;
\ 00000052 C988 LDRH R1,[R1, #+6]
\ 00000054 1022 MOVS R2,#+16
\ 00000056 52EA0112 ORRS R2,R2,R1, LSL #+4
\ 0000005A 1A43 ORRS R2,R2,R3
242 }
243
244 TIMx->CCMR1 = (u16)tmpccmrx;
\ ??TIM_OCInit_4:
\ 0000005C 0583 STRH R5,[R0, #+24]
\ 0000005E 2CE0 B.N ??TIM_OCInit_5
245 }
246 else
247 {
248 if ((TIM_OCInitStruct->TIM_Channel == TIM_Channel_3) ||
249 (TIM_OCInitStruct->TIM_Channel == TIM_Channel_4))
\ ??TIM_OCInit_2:
\ 00000060 022C CMP R4,#+2
\ 00000062 01D0 BEQ.N ??TIM_OCInit_6
\ 00000064 032C CMP R4,#+3
\ 00000066 28D1 BNE.N ??TIM_OCInit_5
250 {
251 tmpccmrx = TIMx->CCMR2;
\ ??TIM_OCInit_6:
\ 00000068 858B LDRH R5,[R0, #+28]
252
253 /* Reset the Output Compare Bits */
254 tmpccmrx &= Tab_OCModeMask[TIM_OCInitStruct->TIM_Channel];
\ 0000006A 33F81440 LDRH R4,[R3, R4, LSL #+1]
\ 0000006E 2C40 ANDS R4,R4,R5
255
256 /* Set the Output Polarity level */
257 tmpccer &= Tab_PolarityMask[TIM_OCInitStruct->TIM_Channel];
\ 00000070 4D88 LDRH R5,[R1, #+2]
\ 00000072 13EB4503 ADDS R3,R3,R5, LSL #+1
\ 00000076 1B89 LDRH R3,[R3, #+8]
\ 00000078 1340 ANDS R3,R3,R2
258
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