📄 cpu.c
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/** ###################################################################
** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.
** Filename : Cpu.C
** Project : EEPROM
** Processor : MC9S12DG128BCPV
** Beantype : MC9S12DG128_112
** Version : Bean 01.167, Driver 01.20, CPU db: 2.87.280
** Datasheet : 9S12DT128BDGV1/D V01.05
** Compiler : Metrowerks HC12 C Compiler
** Date/Time : 2008-3-3, 下午 09:51
** Abstract :
** This bean "MC9S12DG128_112" implements properties, methods,
** and events of the CPU.
** Settings :
**
** Contents :
** EnableInt - void Cpu_EnableInt(void);
** DisableInt - void Cpu_DisableInt(void);
** SetWaitMode - void Cpu_SetWaitMode(void);
** SetStopMode - void Cpu_SetStopMode(void);
**
** (c) Copyright UNIS, spol. s r.o. 1997-2005
** UNIS, spol. s r.o.
** Jundrovska 33
** 624 00 Brno
** Czech Republic
** http : www.processorexpert.com
** mail : info@processorexpert.com
** ###################################################################*/
/* MODULE Cpu. */
#include "Byte1.h"
#include "IEE1.h"
#include "Cpu.h"
#define CGM_DELAY 2559UL
#pragma DATA_SEG DEFAULT
/* Global variables */
volatile byte CCR_reg; /* Current CCR reegister */
byte CpuMode = HIGH_SPEED; /* Current speed mode */
/*
** ===================================================================
** Method : Cpu_Interrupt (bean MC9S12DG128_112)
**
** Description :
** This method is internal. It is used by Processor Expert only.
** ===================================================================
*/
#pragma CODE_SEG __NEAR_SEG NON_BANKED
ISR(Cpu_Interrupt)
{
}
#pragma CODE_SEG DEFAULT
/*
** ===================================================================
** Method : Cpu_DisableInt (bean MC9S12DG128_112)
**
** Description :
** Disable maskable interrupts
** Parameters : None
** Returns : Nothing
** ===================================================================
*/
/*
void Cpu_DisableInt(void)
** This method is implemented as macro in the header module. **
*/
/*
** ===================================================================
** Method : Cpu_EnableInt (bean MC9S12DG128_112)
**
** Description :
** Enable maskable interrupts
** Parameters : None
** Returns : Nothing
** ===================================================================
*/
/*
void Cpu_EnableInt(void)
** This method is implemented as macro in the header module. **
*/
/*
** ===================================================================
** Method : Cpu_SetStopMode (bean MC9S12DG128_112)
**
** Description :
** Set low power mode - Stop mode.
** For more information about the stop mode see
** documentation of this CPU.
** Parameters : None
** Returns : Nothing
** ===================================================================
*/
/*
void Cpu_SetStopMode(void)
** This method is implemented as macro in the header module. **
*/
/*
** ===================================================================
** Method : Cpu_SetWaitMode (bean MC9S12DG128_112)
**
** Description :
** Set low power mode - Wait mode.
** For more information about the wait mode see
** documentation of this CPU.
** Release from Wait mode: Reset or interrupt
** Parameters : None
** Returns : Nothing
** ===================================================================
*/
/*
void Cpu_SetWaitMode(void)
** This method is implemented as macro in the header module. **
*/
/*
** ===================================================================
** Method : _EntryPoint (bean MC9S12DG128_112)
**
** Description :
** This method is internal. It is used by Processor Expert only.
** ===================================================================
*/
extern void _Startup(void); /* Forward declaration of external startup function declared in file Start12.c */
#pragma CODE_SEG __NEAR_SEG NON_BANKED
#define INITRG_ADR 0x0011 /* Register map position register */
#pragma NO_FRAME
#pragma NO_EXIT
void _EntryPoint(void)
{
/*** ### MC9S12DG128BCPV "Cpu" init code ... ***/
/*** PE initialization code after reset ***/
/* Initialization of the registers INITRG, INITRM, INITEE is done to protect them to be written accidentally later by the application */
*(byte*)INITRG_ADR = 0; /* Set the register map position */
asm("nop"); /* nop instruction */
/* INITRM: RAM15=0,RAM14=0,RAM13=1,RAM12=0,RAM11=0,??=0,??=0,RAMHAL=0 */
setReg8(INITRM, 32); /* Set the RAM map position */
/* INITEE: EE15=0,EE14=0,EE13=0,EE12=1,??=1,??=0,??=0,EEON=1 */
setReg8(INITEE, 25); /* Set the EEPROM map position */
/* MISC: ??=0,??=0,??=0,??=0,EXSTR1=1,EXSTR0=1,ROMHM=0,ROMON=1 */
setReg8(MISC, 13);
/* EBICTL: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,ESTR=0 */
setReg8(EBICTL, 0);
/* PEAR: NOACCE=0,??=0,PIPOE=0,NECLK=0,LSTRE=0,RDWE=0,??=0,??=0 */
setReg8(PEAR, 0);
/* CLKSEL: PLLSEL=0,PSTP=0,SYSWAI=0,ROAWAI=0,PLLWAI=0,CWAI=0,RTIWAI=0,COPWAI=0 */
setReg8(CLKSEL, 0); /* Select clock source from XTAL and set bits in CLKSEL reg. */
/* PLLCTL: PLLON=0 */
clrReg8Bits(PLLCTL, 64); /* Disable the PLL */
/* SYNR: ??=0,??=0,SYN5=0,SYN4=0,SYN3=0,SYN2=1,SYN1=0,SYN0=0 */
setReg8(SYNR, 4); /* Set the multiplier register */
/* REFDV: ??=0,??=0,??=0,??=0,REFDV3=0,REFDV2=0,REFDV1=1,REFDV0=1 */
setReg8(REFDV, 3); /* Set the divider register */
/* PLLCTL: CME=0,PLLON=1,AUTO=1,ACQ=1,??=0,PRE=0,PCE=0,SCME=0 */
setReg8(PLLCTL, 112);
while(!CRGFLG_LOCK) {}; /* Wait */
/* CLKSEL: PLLSEL=1 */
setReg8Bits(CLKSEL, 128); /* Select clock source from PLL */
/*** End of PE initialization code after reset ***/
__asm("jmp _Startup"); /* Jump to C startup code */
}
#pragma CODE_SEG DEFAULT
/*
** ===================================================================
** Method : PE_low_level_init (bean MC9S12DG128_112)
**
** Description :
** This method is internal. It is used by Processor Expert only.
** ===================================================================
*/
void PE_low_level_init(void)
{
/* Common initialization of the CPU registers */
/* PPSM: PPSM7=1,PPSM6=1,PPSM5=1,PPSM4=1,PPSM3=1,PPSM2=1,PPSM1=1,PPSM0=1 */
setReg8(PPSM, 255);
/* PERM: PERM7=1,PERM6=1,PERM5=1,PERM4=1,PERM3=1,PERM2=1,PERM1=1,PERM0=1 */
setReg8(PERM, 255);
/* DDRM: DDRM7=0,DDRM6=0,DDRM5=0,DDRM4=0,DDRM3=0,DDRM2=0,DDRM1=0,DDRM0=0 */
setReg8(DDRM, 0);
/* PWMCTL: PSWAI=0,PFRZ=0 */
clrReg8Bits(PWMCTL, 12);
/* PWMSDN: PWMIF=0,PWMIE=0,PWMRSTRT=0,PWMLVL=0,??=0,PWM7IN=0,PWM7INL=0,PWM7ENA=0 */
setReg8(PWMSDN, 0);
/* TSCR1: TSWAI=0,TSFRZ=0 */
clrReg8Bits(TSCR1, 96);
/* ICSYS: SH37=0,SH26=0,SH15=0,SH04=0,TFMOD=0,PACMX=0,BUFEN=0,LATQ=0 */
setReg8(ICSYS, 0);
/* MCCTL: MODMC=1 */
setReg8Bits(MCCTL, 64);
/* ### MC9S12DG128_112 "Cpu" init code ... */
/* ### ByteIO "Byte1" init code ... */
/* ### IntEEPROM "IEE1" init code ... */
IEE1_Init();
/* INTCR: IRQEN=0 */
clrReg8Bits(INTCR, 64); /* Disable the IRQ interrupt. IRQ interrupt is enabled after CPU reset by default. */
__EI(); /* Enable interrupts */
}
/* END Cpu. */
/*
** ###################################################################
**
** This file was created by UNIS Processor Expert 2.96 [03.76]
** for the Freescale HCS12 series of microcontrollers.
**
** ###################################################################
*/
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