📄 io_map.h
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#define DDRA_BIT1 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT1
#define DDRA_BIT2 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT2
#define DDRA_BIT3 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT3
#define DDRA_BIT4 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT4
#define DDRA_BIT5 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT5
#define DDRA_BIT6 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT6
#define DDRA_BIT7 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT7
#define DDRA_BIT0_MASK 1
#define DDRA_BIT1_MASK 2
#define DDRA_BIT2_MASK 4
#define DDRA_BIT3_MASK 8
#define DDRA_BIT4_MASK 16
#define DDRA_BIT5_MASK 32
#define DDRA_BIT6_MASK 64
#define DDRA_BIT7_MASK 128
/*** DDRB - Port B Data Direction Register; 0x00000003 ***/
union {
byte Byte;
struct {
byte BIT0 :1; /* Data Direction Port B Bit 0 */
byte BIT1 :1; /* Data Direction Port B Bit 1 */
byte BIT2 :1; /* Data Direction Port B Bit 2 */
byte BIT3 :1; /* Data Direction Port B Bit 3 */
byte BIT4 :1; /* Data Direction Port B Bit 4 */
byte BIT5 :1; /* Data Direction Port B Bit 5 */
byte BIT6 :1; /* Data Direction Port B Bit 6 */
byte BIT7 :1; /* Data Direction Port B Bit 7 */
} Bits;
} DDRBSTR;
#define DDRB _DDRAB.Overlap_STR.DDRBSTR.Byte
#define DDRB_BIT0 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT0
#define DDRB_BIT1 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT1
#define DDRB_BIT2 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT2
#define DDRB_BIT3 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT3
#define DDRB_BIT4 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT4
#define DDRB_BIT5 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT5
#define DDRB_BIT6 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT6
#define DDRB_BIT7 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT7
#define DDRB_BIT0_MASK 1
#define DDRB_BIT1_MASK 2
#define DDRB_BIT2_MASK 4
#define DDRB_BIT3_MASK 8
#define DDRB_BIT4_MASK 16
#define DDRB_BIT5_MASK 32
#define DDRB_BIT6_MASK 64
#define DDRB_BIT7_MASK 128
} Overlap_STR;
struct {
word BIT0 :1; /* Data Direction Port AB Bit 0 */
word BIT1 :1; /* Data Direction Port AB Bit 1 */
word BIT2 :1; /* Data Direction Port AB Bit 2 */
word BIT3 :1; /* Data Direction Port AB Bit 3 */
word BIT4 :1; /* Data Direction Port AB Bit 4 */
word BIT5 :1; /* Data Direction Port AB Bit 5 */
word BIT6 :1; /* Data Direction Port AB Bit 6 */
word BIT7 :1; /* Data Direction Port AB Bit 7 */
word BIT8 :1; /* Data Direction Port AB Bit 8 */
word BIT9 :1; /* Data Direction Port AB Bit 9 */
word BIT10 :1; /* Data Direction Port AB Bit 10 */
word BIT11 :1; /* Data Direction Port AB Bit 11 */
word BIT12 :1; /* Data Direction Port AB Bit 12 */
word BIT13 :1; /* Data Direction Port AB Bit 13 */
word BIT14 :1; /* Data Direction Port AB Bit 14 */
word BIT15 :1; /* Data Direction Port AB Bit 15 */
} Bits;
} DDRABSTR;
extern volatile DDRABSTR _DDRAB @(REG_BASE + 0x00000002);
#define DDRAB _DDRAB.Word
#define DDRAB_BIT0 _DDRAB.Bits.BIT0
#define DDRAB_BIT1 _DDRAB.Bits.BIT1
#define DDRAB_BIT2 _DDRAB.Bits.BIT2
#define DDRAB_BIT3 _DDRAB.Bits.BIT3
#define DDRAB_BIT4 _DDRAB.Bits.BIT4
#define DDRAB_BIT5 _DDRAB.Bits.BIT5
#define DDRAB_BIT6 _DDRAB.Bits.BIT6
#define DDRAB_BIT7 _DDRAB.Bits.BIT7
#define DDRAB_BIT8 _DDRAB.Bits.BIT8
#define DDRAB_BIT9 _DDRAB.Bits.BIT9
#define DDRAB_BIT10 _DDRAB.Bits.BIT10
#define DDRAB_BIT11 _DDRAB.Bits.BIT11
#define DDRAB_BIT12 _DDRAB.Bits.BIT12
#define DDRAB_BIT13 _DDRAB.Bits.BIT13
#define DDRAB_BIT14 _DDRAB.Bits.BIT14
#define DDRAB_BIT15 _DDRAB.Bits.BIT15
#define DDRAB_BIT0_MASK 1
#define DDRAB_BIT1_MASK 2
#define DDRAB_BIT2_MASK 4
#define DDRAB_BIT3_MASK 8
#define DDRAB_BIT4_MASK 16
#define DDRAB_BIT5_MASK 32
#define DDRAB_BIT6_MASK 64
#define DDRAB_BIT7_MASK 128
#define DDRAB_BIT8_MASK 256
#define DDRAB_BIT9_MASK 512
#define DDRAB_BIT10_MASK 1024
#define DDRAB_BIT11_MASK 2048
#define DDRAB_BIT12_MASK 4096
#define DDRAB_BIT13_MASK 8192
#define DDRAB_BIT14_MASK 16384
#define DDRAB_BIT15_MASK 32768
/*** PORTE - Port E Register; 0x00000008 ***/
typedef union {
byte Byte;
struct {
byte BIT0 :1; /* Port E Bit 0 */
byte BIT1 :1; /* Port E Bit 1 */
byte BIT2 :1; /* Port E Bit 2 */
byte BIT3 :1; /* Port E Bit 3 */
byte BIT4 :1; /* Port E Bit 4 */
byte BIT5 :1; /* Port E Bit 5 */
byte BIT6 :1; /* Port E Bit 6 */
byte BIT7 :1; /* Port E Bit 7 */
} Bits;
} PORTESTR;
extern volatile PORTESTR _PORTE @(REG_BASE + 0x00000008);
#define PORTE _PORTE.Byte
#define PORTE_BIT0 _PORTE.Bits.BIT0
#define PORTE_BIT1 _PORTE.Bits.BIT1
#define PORTE_BIT2 _PORTE.Bits.BIT2
#define PORTE_BIT3 _PORTE.Bits.BIT3
#define PORTE_BIT4 _PORTE.Bits.BIT4
#define PORTE_BIT5 _PORTE.Bits.BIT5
#define PORTE_BIT6 _PORTE.Bits.BIT6
#define PORTE_BIT7 _PORTE.Bits.BIT7
#define PORTE_BIT0_MASK 1
#define PORTE_BIT1_MASK 2
#define PORTE_BIT2_MASK 4
#define PORTE_BIT3_MASK 8
#define PORTE_BIT4_MASK 16
#define PORTE_BIT5_MASK 32
#define PORTE_BIT6_MASK 64
#define PORTE_BIT7_MASK 128
/*** DDRE - Port E Data Direction Register; 0x00000009 ***/
typedef union {
byte Byte;
struct {
byte :1;
byte :1;
byte BIT2 :1; /* Data Direction Port E Bit 2 */
byte BIT3 :1; /* Data Direction Port E Bit 3 */
byte BIT4 :1; /* Data Direction Port E Bit 4 */
byte BIT5 :1; /* Data Direction Port E Bit 5 */
byte BIT6 :1; /* Data Direction Port E Bit 6 */
byte BIT7 :1; /* Data Direction Port E Bit 7 */
} Bits;
struct {
byte :1;
byte :1;
byte grpBIT_2 :6;
} MergedBits;
} DDRESTR;
extern volatile DDRESTR _DDRE @(REG_BASE + 0x00000009);
#define DDRE _DDRE.Byte
#define DDRE_BIT2 _DDRE.Bits.BIT2
#define DDRE_BIT3 _DDRE.Bits.BIT3
#define DDRE_BIT4 _DDRE.Bits.BIT4
#define DDRE_BIT5 _DDRE.Bits.BIT5
#define DDRE_BIT6 _DDRE.Bits.BIT6
#define DDRE_BIT7 _DDRE.Bits.BIT7
#define DDRE_BIT_2 _DDRE.MergedBits.grpBIT_2
#define DDRE_BIT DDRE_BIT_2
#define DDRE_BIT2_MASK 4
#define DDRE_BIT3_MASK 8
#define DDRE_BIT4_MASK 16
#define DDRE_BIT5_MASK 32
#define DDRE_BIT6_MASK 64
#define DDRE_BIT7_MASK 128
#define DDRE_BIT_2_MASK 252
#define DDRE_BIT_2_BITNUM 2
/*** PEAR - Port E Assignment Register; 0x0000000A ***/
typedef union {
byte Byte;
struct {
byte :1;
byte :1;
byte RDWE :1; /* Read / Write Enable */
byte LSTRE :1; /* Low Strobe (LSTRB) Enable */
byte NECLK :1; /* No External E Clock */
byte PIPOE :1; /* Pipe Status Signal Output Enable */
byte :1;
byte NOACCE :1; /* CPU No Access Output Enable */
} Bits;
} PEARSTR;
extern volatile PEARSTR _PEAR @(REG_BASE + 0x0000000A);
#define PEAR _PEAR.Byte
#define PEAR_RDWE _PEAR.Bits.RDWE
#define PEAR_LSTRE _PEAR.Bits.LSTRE
#define PEAR_NECLK _PEAR.Bits.NECLK
#define PEAR_PIPOE _PEAR.Bits.PIPOE
#define PEAR_NOACCE _PEAR.Bits.NOACCE
#define PEAR_RDWE_MASK 4
#define PEAR_LSTRE_MASK 8
#define PEAR_NECLK_MASK 16
#define PEAR_PIPOE_MASK 32
#define PEAR_NOACCE_MASK 128
/*** MODE - Mode Register; 0x0000000B ***/
typedef union {
byte Byte;
struct {
byte EME :1; /* Emulate Port E */
byte EMK :1; /* Emulate Port K */
byte :1;
byte IVIS :1; /* Internal Visibility */
byte :1;
byte MODA :1; /* Mode Select Bit A */
byte MODB :1; /* Mode Select Bit B */
byte MODC :1; /* Mode Select Bit C */
} Bits;
struct {
byte :1;
byte :1;
byte :1;
byte :1;
byte :1;
byte grpMODx :3;
} MergedBits;
} MODESTR;
extern volatile MODESTR _MODE @(REG_BASE + 0x0000000B);
#define MODE _MODE.Byte
#define MODE_EME _MODE.Bits.EME
#define MODE_EMK _MODE.Bits.EMK
#define MODE_IVIS _MODE.Bits.IVIS
#define MODE_MODA _MODE.Bits.MODA
#define MODE_MODB _MODE.Bits.MODB
#define MODE_MODC _MODE.Bits.MODC
#define MODE_MODx _MODE.MergedBits.grpMODx
#define MODE_EME_MASK 1
#define MODE_EMK_MASK 2
#define MODE_IVIS_MASK 8
#define MODE_MODA_MASK 32
#define MODE_MODB_MASK 64
#define MODE_MODC_MASK 128
#define MODE_MODx_MASK 224
#define MODE_MODx_BITNUM 5
/*** PUCR - Pull-Up Control Register; 0x0000000C ***/
typedef union {
byte Byte;
struct {
byte PUPAE :1; /* Pull-Up Port A Enable */
byte PUPBE :1; /* Pull-Up Port B Enable */
byte :1;
byte :1;
byte PUPEE :1; /* Pull-Up Port E Enable */
byte :1;
byte :1;
byte PUPKE :1; /* Pull-Up Port K Enable */
} Bits;
} PUCRSTR;
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