📄 dm642init.asm
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;******************************************************************************
;* TMS320C6x C/C++ Codegen PC v5.1.0 *
;* Date/Time created: Mon Aug 13 17:31:58 2007 *
;******************************************************************************
.compiler_opts --endian=little --mem_model:code=far --mem_model:data=far --predefine_memory_model_macros --quiet --silicon_version=6400
;******************************************************************************
;* GLOBAL FILE PARAMETERS *
;* *
;* Architecture : TMS320C64xx *
;* Optimization : Enabled at level 3 *
;* Optimizing for : Speed *
;* Based on options: -o3, no -ms *
;* Endian : Little *
;* Interrupt Thrshld : Disabled *
;* Data Access Model : Far *
;* Pipelining : Enabled *
;* Speculate Loads : Disabled *
;* Memory Aliases : Presume not aliases (optimistic) *
;* Debug Info : Optimized w/Profiling Info *
;* *
;******************************************************************************
.asg A15, FP
.asg B14, DP
.asg B15, SP
.global $bss
DW$CU .dwtag DW_TAG_compile_unit
.dwattr DW$CU, DW_AT_name("dm642init.c")
.dwattr DW$CU, DW_AT_producer("TMS320C6x C/C++ Codegen PC v5.1.0 Copyright (c) 1996-2005 Texas Instruments Incorporated")
.dwattr DW$CU, DW_AT_stmt_list(0x00)
.dwattr DW$CU, DW_AT_TI_VERSION(0x01)
;*****************************************************************************
;* CINIT RECORDS *
;*****************************************************************************
.sect ".cinit"
.align 8
.field IR_1,32
.field _LinkStr+0,32
.field SL1,32 ; _LinkStr[0] @ 0
.field SL2,32 ; _LinkStr[1] @ 32
.field SL3,32 ; _LinkStr[2] @ 64
.field SL4,32 ; _LinkStr[3] @ 96
.field SL5,32 ; _LinkStr[4] @ 128
IR_1: .set 20
DW$1 .dwtag DW_TAG_subprogram, DW_AT_name("printf"), DW_AT_symbol_name("_printf")
.dwattr DW$1, DW_AT_type(*DW$T$10)
.dwattr DW$1, DW_AT_declaration(0x01)
.dwattr DW$1, DW_AT_external(0x01)
DW$2 .dwtag DW_TAG_formal_parameter, DW_AT_type(*DW$T$50)
DW$3 .dwtag DW_TAG_unspecified_parameters
.dwendtag DW$1
DW$4 .dwtag DW_TAG_subprogram, DW_AT_name("mmCopy"), DW_AT_symbol_name("_mmCopy")
.dwattr DW$4, DW_AT_declaration(0x01)
.dwattr DW$4, DW_AT_external(0x01)
DW$5 .dwtag DW_TAG_formal_parameter, DW_AT_type(*DW$T$3)
DW$6 .dwtag DW_TAG_formal_parameter, DW_AT_type(*DW$T$3)
DW$7 .dwtag DW_TAG_formal_parameter, DW_AT_type(*DW$T$20)
.dwendtag DW$4
DW$8 .dwtag DW_TAG_subprogram, DW_AT_name("EVMDM642_init"), DW_AT_symbol_name("_EVMDM642_init")
.dwattr DW$8, DW_AT_declaration(0x01)
.dwattr DW$8, DW_AT_external(0x01)
DW$9 .dwtag DW_TAG_subprogram, DW_AT_name("EVMDM642_LED_init"), DW_AT_symbol_name("_EVMDM642_LED_init")
.dwattr DW$9, DW_AT_declaration(0x01)
.dwattr DW$9, DW_AT_external(0x01)
DW$10 .dwtag DW_TAG_subprogram, DW_AT_name("MDIO_phyRegWrite"), DW_AT_symbol_name("_MDIO_phyRegWrite")
.dwattr DW$10, DW_AT_type(*DW$T$20)
.dwattr DW$10, DW_AT_declaration(0x01)
.dwattr DW$10, DW_AT_external(0x01)
DW$11 .dwtag DW_TAG_formal_parameter, DW_AT_type(*DW$T$20)
DW$12 .dwtag DW_TAG_formal_parameter, DW_AT_type(*DW$T$20)
DW$13 .dwtag DW_TAG_formal_parameter, DW_AT_type(*DW$T$47)
.dwendtag DW$10
_LinkStr: .usect ".far",20,8
DW$14 .dwtag DW_TAG_variable, DW_AT_name("LinkStr"), DW_AT_symbol_name("_LinkStr")
.dwattr DW$14, DW_AT_type(*DW$T$64)
.dwattr DW$14, DW_AT_location[DW_OP_addr _LinkStr]
_bMacAddr: .usect ".far",8,8
DW$15 .dwtag DW_TAG_variable, DW_AT_name("bMacAddr"), DW_AT_symbol_name("_bMacAddr")
.dwattr DW$15, DW_AT_type(*DW$T$42)
.dwattr DW$15, DW_AT_location[DW_OP_addr _bMacAddr]
; C:\CCStudio_v3.1\C6000\cgtools\bin\opt6x.exe C:\DOCUME~1\new\LOCALS~1\Temp\TI0642 C:\DOCUME~1\new\LOCALS~1\Temp\TI0644
.sect ".text"
.global _dm642_init
DW$16 .dwtag DW_TAG_subprogram, DW_AT_name("dm642_init"), DW_AT_symbol_name("_dm642_init")
.dwattr DW$16, DW_AT_low_pc(_dm642_init)
.dwattr DW$16, DW_AT_high_pc(0x00)
.dwattr DW$16, DW_AT_begin_file("dm642init.c")
.dwattr DW$16, DW_AT_begin_line(0x25)
.dwattr DW$16, DW_AT_begin_column(0x06)
.dwattr DW$16, DW_AT_frame_base[DW_OP_breg31 8]
.dwattr DW$16, DW_AT_skeletal(0x01)
.dwpsn "dm642init.c",38,1
;******************************************************************************
;* FUNCTION NAME: _dm642_init *
;* *
;* Regs Modified : A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,B0,B1,B2,B3,B4,B5,B6, *
;* B7,B8,B9,SP,A16,A17,A18,A19,A20,A21,A22,A23,A24, *
;* A25,A26,A27,A28,A29,A30,A31,B16,B17,B18,B19,B20, *
;* B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31 *
;* Regs Used : A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,B0,B1,B2,B3,B4,B5,B6, *
;* B7,B8,B9,SP,A16,A17,A18,A19,A20,A21,A22,A23,A24, *
;* A25,A26,A27,A28,A29,A30,A31,B16,B17,B18,B19,B20, *
;* B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31 *
;* Local Frame Size : 0 Args + 0 Auto + 4 Save = 4 byte *
;******************************************************************************
_dm642_init:
;** --------------------------------------------------------------------------*
MVKL .S1 0x1848200,A3 ; |413|
|| STW .D2T2 B3,*SP--(8) ; |38|
|| MVKL .S2 0x1848200,B4 ; |413|
MVKH .S1 0x1848200,A3 ; |413|
|| MVKH .S2 0x1848200,B4 ; |413|
LDW .D1T1 *A3,A3 ; |413|
|| MVKL .S2 0x1848200,B5 ; |414|
NOP 3
MVKH .S2 0x1848200,B5 ; |414|
OR .L1 1,A3,A3 ; |413|
MVKL .S1 0x1848200,A3 ; |414| (P) <0,0>
|| STW .D2T1 A3,*B4 ; |413|
MVKH .S1 0x1848200,A3 ; |414| (P) <0,1>
|| LDW .D2T2 *B5,B4 ; |414|
NOP 4
AND .L2 1,B4,B0 ; |414|
[ B0] BNOP .S1 L4,3 ; |414|
|| [!B0] MVK .S2 0x1,B0
|| [!B0] LDW .D1T1 *A3,A4 ; |414| (P) <0,2> ^
|| MV .L2 B0,B1 ; guard predicate rewrite
[!B1] MVKL .S1 0x1848200,A3 ; |414| (P) <1,0>
[!B1] AND .L1 1,A4,A0 ; |414| (P) <0,7> ^
; BRANCHCC OCCURS {L4} ; |414|
;*----------------------------------------------------------------------------*
;* SOFTWARE PIPELINE INFORMATION
;*
;* Loop source line : 414
;* Loop closing brace source line : 414
;* Known Minimum Trip Count : 1
;* Known Max Trip Count Factor : 1
;* Loop Carried Dependency Bound(^) : 7
;* Unpartitioned Resource Bound : 2
;* Partitioned Resource Bound(*) : 2
;* Resource Partition:
;* A-side B-side
;* .L units 0 0
;* .S units 2* 1
;* .D units 1 0
;* .M units 0 0
;* .X cross paths 0 0
;* .T address paths 1 0
;* Long read paths 0 0
;* Long write paths 0 0
;* Logical ops (.LS) 0 0 (.L or .S unit)
;* Addition ops (.LSD) 1 1 (.L or .S or .D unit)
;* Bound(.L .S .LS) 1 1
;* Bound(.L .S .D .LS .LSD) 2* 1
;*
;* Searching for software pipeline schedule at ...
;* ii = 7 Schedule found with 3 iterations in parallel
;*
;* Register Usage Table:
;* +-----------------------------------------------------------------+
;* |AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA|BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB|
;* |00000000001111111111222222222233|00000000001111111111222222222233|
;* |01234567890123456789012345678901|01234567890123456789012345678901|
;* |--------------------------------+--------------------------------|
;* 0: |* ** |* |
;* 1: | ** |* |
;* 2: | * |* |
;* 3: | * |* |
;* 4: | * |* |
;* 5: | * |* |
;* 6: | * |* |
;* +-----------------------------------------------------------------+
;*
;* Done
;*
;* Loop is interruptible
;* Collapsed epilog stages : 2
;* Prolog not removed
;* Collapsed prolog stages : 0
;*
;* Minimum required memory pad : 0 bytes
;*
;* Minimum safe trip count : 1
;*----------------------------------------------------------------------------*
;* SETUP CODE
;*
;* MVK 0x1,B0
;* ZERO A4
;*
;* SINGLE SCHEDULED ITERATION
;*
;* C65:
;* 0 MVKL .S1 0x1848200,A3 ; |414|
;* 1 MVKH .S1 0x1848200,A3 ; |414|
;* 2 [ B0] LDW .D1T1 *A3,A4 ; |414| ^
;* 3 NOP 4
;* 7 AND .L1 1,A4,A0 ; |414| ^
;* 8 [ A0] ZERO .L2 B0 ; |414| ^
;* 9 [ B0] B .S2 C65 ; |414|
;* 10 NOP 5
;* 15 ; BRANCHCC OCCURS {C65} ; |414|
;*----------------------------------------------------------------------------*
L1: ; PIPED LOOP PROLOG
;** --------------------------------------------------------------------------*
L2: ; PIPED LOOP KERNEL
DW$L$_dm642_init$3$B:
[ A0] ZERO .L2 B0 ; |414| <0,8> ^
|| MVKH .S1 0x1848200,A3 ; |414| <1,1>
[ B0] BNOP .S2 L2,4 ; |414| <0,9>
|| [ B0] LDW .D1T1 *A3,A4 ; |414| <1,2> ^
AND .L1 1,A4,A0 ; |414| <1,7> ^
|| MVKL .S1 0x1848200,A3 ; |414| <2,0>
DW$L$_dm642_init$3$E:
;** --------------------------------------------------------------------------*
L3: ; PIPED LOOP EPILOG
;** --------------------------------------------------------------------------*
L4:
MVKL .S1 0x1848204,A3 ; |413|
|| MVKL .S2 0x1848204,B4 ; |413|
MVKH .S1 0x1848204,A3 ; |413|
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