📄 jpegmain.asm
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MVKH .S1 0x1848200,A3 ; |414| (P) <0,1>
|| LDW .D2T2 *B5,B4 ; |414|
NOP 4
AND .L2 1,B4,B0 ; |414|
[ B0] BNOP .S1 L4,3 ; |414|
|| [!B0] MVK .S2 0x1,B0
|| [!B0] LDW .D1T1 *A3,A4 ; |414| (P) <0,2> ^
|| MV .L2 B0,B1 ; guard predicate rewrite
[!B1] MVKL .S1 0x1848200,A3 ; |414| (P) <1,0>
[!B1] AND .L1 1,A4,A0 ; |414| (P) <0,7> ^
; BRANCHCC OCCURS {L4} ; |414|
;*----------------------------------------------------------------------------*
;* SOFTWARE PIPELINE INFORMATION
;*
;* Loop source line : 414
;* Loop closing brace source line : 414
;* Known Minimum Trip Count : 1
;* Known Max Trip Count Factor : 1
;* Loop Carried Dependency Bound(^) : 7
;* Unpartitioned Resource Bound : 2
;* Partitioned Resource Bound(*) : 2
;* Resource Partition:
;* A-side B-side
;* .L units 0 0
;* .S units 2* 1
;* .D units 1 0
;* .M units 0 0
;* .X cross paths 0 0
;* .T address paths 1 0
;* Long read paths 0 0
;* Long write paths 0 0
;* Logical ops (.LS) 0 0 (.L or .S unit)
;* Addition ops (.LSD) 1 1 (.L or .S or .D unit)
;* Bound(.L .S .LS) 1 1
;* Bound(.L .S .D .LS .LSD) 2* 1
;*
;* Searching for software pipeline schedule at ...
;* ii = 7 Schedule found with 3 iterations in parallel
;*
;* Register Usage Table:
;* +-----------------------------------------------------------------+
;* |AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA|BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB|
;* |00000000001111111111222222222233|00000000001111111111222222222233|
;* |01234567890123456789012345678901|01234567890123456789012345678901|
;* |--------------------------------+--------------------------------|
;* 0: |* ** |* |
;* 1: | ** |* |
;* 2: | * |* |
;* 3: | * |* |
;* 4: | * |* |
;* 5: | * |* |
;* 6: | * |* |
;* +-----------------------------------------------------------------+
;*
;* Done
;*
;* Loop is interruptible
;* Collapsed epilog stages : 2
;* Prolog not removed
;* Collapsed prolog stages : 0
;*
;* Minimum required memory pad : 0 bytes
;*
;* Minimum safe trip count : 1
;*----------------------------------------------------------------------------*
;* SETUP CODE
;*
;* MVK 0x1,B0
;* ZERO A4
;*
;* SINGLE SCHEDULED ITERATION
;*
;* C67:
;* 0 MVKL .S1 0x1848200,A3 ; |414|
;* 1 MVKH .S1 0x1848200,A3 ; |414|
;* 2 [ B0] LDW .D1T1 *A3,A4 ; |414| ^
;* 3 NOP 4
;* 7 AND .L1 1,A4,A0 ; |414| ^
;* 8 [ A0] ZERO .L2 B0 ; |414| ^
;* 9 [ B0] B .S2 C67 ; |414|
;* 10 NOP 5
;* 15 ; BRANCHCC OCCURS {C67} ; |414|
;*----------------------------------------------------------------------------*
L1: ; PIPED LOOP PROLOG
;** --------------------------------------------------------------------------*
L2: ; PIPED LOOP KERNEL
DW$L$_main$5$B:
[ A0] ZERO .L2 B0 ; |414| <0,8> ^
|| MVKH .S1 0x1848200,A3 ; |414| <1,1>
[ B0] BNOP .S2 L2,4 ; |414| <0,9>
|| [ B0] LDW .D1T1 *A3,A4 ; |414| <1,2> ^
AND .L1 1,A4,A0 ; |414| <1,7> ^
|| MVKL .S1 0x1848200,A3 ; |414| <2,0>
DW$L$_main$5$E:
;** --------------------------------------------------------------------------*
L3: ; PIPED LOOP EPILOG
;** --------------------------------------------------------------------------*
L4:
MVKL .S1 0x1848204,A3 ; |413|
|| MVKL .S2 0x1848204,B4 ; |413|
MVKH .S1 0x1848204,A3 ; |413|
|| MVKH .S2 0x1848204,B4 ; |413|
LDW .D1T1 *A3,A3 ; |413|
|| MVKL .S2 0x1848204,B5 ; |414|
NOP 3
MVKH .S2 0x1848204,B5 ; |414|
OR .L1 1,A3,A3 ; |413|
MVKL .S1 0x1848204,A3 ; |414| (P) <0,0>
|| STW .D2T1 A3,*B4 ; |413|
MVKH .S1 0x1848204,A3 ; |414| (P) <0,1>
|| LDW .D2T2 *B5,B4 ; |414|
NOP 4
AND .L2 1,B4,B0 ; |414|
[ B0] BNOP .S1 L8,3 ; |414|
|| [!B0] MVK .S2 0x1,B0
|| [!B0] LDW .D1T1 *A3,A4 ; |414| (P) <0,2> ^
|| MV .L2 B0,B1 ; guard predicate rewrite
[!B1] MVKL .S1 0x1848204,A3 ; |414| (P) <1,0>
[!B1] AND .L1 1,A4,A0 ; |414| (P) <0,7> ^
; BRANCHCC OCCURS {L8} ; |414|
;*----------------------------------------------------------------------------*
;* SOFTWARE PIPELINE INFORMATION
;*
;* Loop source line : 414
;* Loop closing brace source line : 414
;* Known Minimum Trip Count : 1
;* Known Max Trip Count Factor : 1
;* Loop Carried Dependency Bound(^) : 7
;* Unpartitioned Resource Bound : 2
;* Partitioned Resource Bound(*) : 2
;* Resource Partition:
;* A-side B-side
;* .L units 0 0
;* .S units 2* 1
;* .D units 1 0
;* .M units 0 0
;* .X cross paths 0 0
;* .T address paths 1 0
;* Long read paths 0 0
;* Long write paths 0 0
;* Logical ops (.LS) 0 0 (.L or .S unit)
;* Addition ops (.LSD) 1 1 (.L or .S or .D unit)
;* Bound(.L .S .LS) 1 1
;* Bound(.L .S .D .LS .LSD) 2* 1
;*
;* Searching for software pipeline schedule at ...
;* ii = 7 Schedule found with 3 iterations in parallel
;*
;* Register Usage Table:
;* +-----------------------------------------------------------------+
;* |AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA|BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB|
;* |00000000001111111111222222222233|00000000001111111111222222222233|
;* |01234567890123456789012345678901|01234567890123456789012345678901|
;* |--------------------------------+--------------------------------|
;* 0: |* ** |* |
;* 1: | ** |* |
;* 2: | * |* |
;* 3: | * |* |
;* 4: | * |* |
;* 5: | * |* |
;* 6: | * |* |
;* +-----------------------------------------------------------------+
;*
;* Done
;*
;* Loop is interruptible
;* Collapsed epilog stages : 2
;* Prolog not removed
;* Collapsed prolog stages : 0
;*
;* Minimum required memory pad : 0 bytes
;*
;* Minimum safe trip count : 1
;*----------------------------------------------------------------------------*
;* SETUP CODE
;*
;* MVK 0x1,B0
;* ZERO A4
;*
;* SINGLE SCHEDULED ITERATION
;*
;* C32:
;* 0 MVKL .S1 0x1848204,A3 ; |414|
;* 1 MVKH .S1 0x1848204,A3 ; |414|
;* 2 [ B0] LDW .D1T1 *A3,A4 ; |414| ^
;* 3 NOP 4
;* 7 AND .L1 1,A4,A0 ; |414| ^
;* 8 [ A0] ZERO .L2 B0 ; |414| ^
;* 9 [ B0] B .S2 C32 ; |414|
;* 10 NOP 5
;* 15 ; BRANCHCC OCCURS {C32} ; |414|
;*----------------------------------------------------------------------------*
L5: ; PIPED LOOP PROLOG
;** --------------------------------------------------------------------------*
L6: ; PIPED LOOP KERNEL
DW$L$_main$9$B:
[ A0] ZERO .L2 B0 ; |414| <0,8> ^
|| MVKH .S1 0x1848204,A3 ; |414| <1,1>
[ B0] BNOP .S2 L6,4 ; |414| <0,9>
|| [ B0] LDW .D1T1 *A3,A4 ; |414| <1,2> ^
AND .L1 1,A4,A0 ; |414| <1,7> ^
|| MVKL .S1 0x1848204,A3 ; |414| <2,0>
DW$L$_main$9$E:
;** --------------------------------------------------------------------------*
L7: ; PIPED LOOP EPILOG
;** --------------------------------------------------------------------------*
L8:
MVKL .S2 _DAT_open,B5 ; |25|
MVKH .S2 _DAT_open,B5 ; |25|
CALL .S2 B5 ; |25|
ADDKPC .S2 RL4,B3,1 ; |25|
MVK .L1 0x1,A6 ; |25|
MVK .L2 0x3,B4 ; |25|
ZERO .S1 A4 ; |25|
RL4: ; CALL OCCURS {_DAT_open} ; |25|
;** --------------------------------------------------------------------------*
MVKL .S2 0x184200c,B4 ; |428|
MVKH .S2 0x184200c,B4 ; |428|
LDW .D2T2 *B4,B4 ; |428|
MVKL .S1 0x184200c,A3 ; |428|
MVKH .S1 0x184200c,A3 ; |428|
MVKL .S2 0x1842004,B5 ; |428|
MVKH .S2 0x1842004,B5 ; |428|
OR .L2 7,B4,B4 ; |428|
STW .D1T2 B4,*A3 ; |428|
LDW .D2T2 *B5,B4 ; |428|
MVKL .S1 0x1842004,A31 ; |428|
MVKH .S1 0x1842004,A31 ; |428|
ZERO .L1 A4 ; |424|
MVKH .S1 0x1840000,A4 ; |424|
OR .L2 7,B4,B4 ; |428|
STW .D1T2 B4,*A31 ; |428|
|| MVKL .S1 _ACPY2_6X1X_init,A3 ; |424|
LDW .D1T1 *A4,A4 ; |424|
|| MVKH .S1 _ACPY2_6X1X_init,A3 ; |424|
ZERO .L2 B4 ; |424|
CALL .S2X A3 ; |424|
MVKH .S2 0x1840000,B4 ; |424|
ADDKPC .S2 RL5,B3,0 ; |424|
EXTU .S1 A4,3,3,A4 ; |424|
SET .S1 A4,29,29,A4 ; |424|
STW .D2T1 A4,*B4 ; |424|
RL5: ; CALL OCCURS {_ACPY2_6X1X_init} ; |424|
MVKL .S1 _DMAN_init,A3 ; |33|
MVKH .S1 _DMAN_init,A3 ; |33|
NOP 1
CALL .S2X A3 ; |33|
ADDKPC .S2 RL6,B3,4 ; |33|
RL6: ; CALL OCCURS {_DMAN_init} ; |33|
MVKL .S1 _DMAN_setup,A3 ; |34|
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