📄 emif_com_map.mrp
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WARNING:PhysDesignRules:372 - Gated clock. Clock net un1_TEA_19_0_a2 is sourced
by a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.WARNING:PhysDesignRules:372 - Gated clock. Clock net un1_TEA_20_0_a2 is sourced
by a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.WARNING:PhysDesignRules:367 - The signal <CLKOUT2_IBUF> is incomplete. The
signal does not drive any load pins in the design.Section 3 - Informational-------------------------INFO:MapLib:562 - No environment variables are currently set.INFO:LIT:244 - All of the single ended outputs in this design are using slew
rate limited output drivers. The delay on speed critical single ended outputs
can be dramatically reduced by designating them as fast outputs in the
schematic.Section 4 - Removed Logic Summary--------------------------------- 25 block(s) removed 1 block(s) optimized away 13 signal(s) removedSection 5 - Removed Logic-------------------------The trimmed logic reported below is either: 1. part of a cycle 2. part of disabled logic 3. a side-effect of other trimmed logicThe signal "EXT_INT[0]" is unused and has been removed. Unused block "EXT_INT_obuft[0]" (TRI) removed. The signal "VCC" is unused and has been removed. Unused block "VCC" (ONE) removed.The signal "EXT_INT[1]" is unused and has been removed. Unused block "EXT_INT_obuft[1]" (TRI) removed.The signal "EXT_INT[2]" is unused and has been removed. Unused block "EXT_INT_obuft[2]" (TRI) removed.The signal "EXT_INT[3]" is unused and has been removed. Unused block "EXT_INT_obuft[3]" (TRI) removed.The signal "LED_OUT[0]" is unused and has been removed. Unused block "LED_OUT_obuft[0]" (TRI) removed.The signal "LED_OUT[1]" is unused and has been removed. Unused block "LED_OUT_obuft[1]" (TRI) removed.The signal "LED_OUT[2]" is unused and has been removed. Unused block "LED_OUT_obuft[2]" (TRI) removed.The signal "LED_OUT[3]" is unused and has been removed. Unused block "LED_OUT_obuft[3]" (TRI) removed.The signal "LED_OUT[4]" is unused and has been removed. Unused block "LED_OUT_obuft[4]" (TRI) removed.The signal "LED_OUT[5]" is unused and has been removed. Unused block "LED_OUT_obuft[5]" (TRI) removed.The signal "LED_OUT[6]" is unused and has been removed. Unused block "LED_OUT_obuft[6]" (TRI) removed.The signal "LED_OUT[7]" is unused and has been removed. Unused block "LED_OUT_obuft[7]" (TRI) removed.Unused block "EXT_INT[0]" (PAD) removed.Unused block "EXT_INT[1]" (PAD) removed.Unused block "EXT_INT[2]" (PAD) removed.Unused block "EXT_INT[3]" (PAD) removed.Unused block "LED_OUT[0]" (PAD) removed.Unused block "LED_OUT[1]" (PAD) removed.Unused block "LED_OUT[2]" (PAD) removed.Unused block "LED_OUT[3]" (PAD) removed.Unused block "LED_OUT[4]" (PAD) removed.Unused block "LED_OUT[5]" (PAD) removed.Unused block "LED_OUT[6]" (PAD) removed.Unused block "LED_OUT[7]" (PAD) removed.Optimized Block(s):TYPE BLOCKGND GNDTo enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.Section 6 - IOB Properties--------------------------+------------------------------------------------------------------------------------------------------------------------+| IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB || | | | | Strength | Rate | | | Delay |+------------------------------------------------------------------------------------------------------------------------+| CLKOUT2 | GCLKIOB | INPUT | LVTTL | | | | | || AOE | IOB | INPUT | LVTTL | | | | | || ARE | IOB | INPUT | LVTTL | | | | | || AWE | IOB | INPUT | LVTTL | | | | | || CE2 | IOB | INPUT | LVTTL | | | | | || RST | IOB | INPUT | LVTTL | | | | | || TEA[0] | IOB | INPUT | LVTTL | | | | | || TEA[1] | IOB | INPUT | LVTTL | | | | | || TEA[2] | IOB | INPUT | LVTTL | | | | | || TEA[3] | IOB | INPUT | LVTTL | | | | | || TED[0] | IOB | BIDIR | LVTTL | 12 | SLOW | | | || TED[1] | IOB | BIDIR | LVTTL | 12 | SLOW | | | || TED[2] | IOB | BIDIR | LVTTL | 12 | SLOW | | | || TED[3] | IOB | BIDIR | LVTTL | 12 | SLOW | | | || TED[4] | IOB | BIDIR | LVTTL | 12 | SLOW | | | || TED[5] | IOB | BIDIR | LVTTL | 12 | SLOW | | | || TED[6] | IOB | BIDIR | LVTTL | 12 | SLOW | | | || TED[7] | IOB | BIDIR | LVTTL | 12 | SLOW | | | || TED[8] | IOB | BIDIR | LVTTL | 12 | SLOW | | | || TED[9] | IOB | BIDIR | LVTTL | 12 | SLOW | | | || TED[10] | IOB | BIDIR | LVTTL | 12 | SLOW | | | || TED[11] | IOB | BIDIR | LVTTL | 12 | SLOW | | | || TED[12] | IOB | BIDIR | LVTTL | 12 | SLOW | | | || TED[13] | IOB | BIDIR | LVTTL | 12 | SLOW | | | || TED[14] | IOB | BIDIR | LVTTL | 12 | SLOW | | | || TED[15] | IOB | BIDIR | LVTTL | 12 | SLOW | | | |+------------------------------------------------------------------------------------------------------------------------+Section 7 - RPMs----------------Section 8 - Guide Report------------------------Guide not run on this design.Section 9 - Area Group and Partition Summary--------------------------------------------Partition Implementation Status------------------------------- No Partitions were found in this design.-------------------------------Area Group Information---------------------- No area groups were found in this design.----------------------Section 10 - Modular Design Summary-----------------------------------Modular Design not used for this design.Section 11 - Timing Report--------------------------No timing report for this architecture.Section 12 - Configuration String Details-----------------------------------------Use the "-detail" map option to print out Configuration Strings⌨️ 快捷键说明
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