emif_com_map.map

实现FPGA与DSP之间通信的接口,利用DSP的标准EMIF接口

Release 9.1i Map J.30
Xilinx Map Application Log File for Design 'EMIF_COM'

Design Information
------------------
Command Line   : D:\EDA\Xilinx91i\bin\nt\map.exe -ise
E:/ISE_Prj/EMIF_COM/EMIF_COM.ise -intstyle ise -p xc2s200-pq208-5 -cm area -pr b
-k 4 -c 100 -tx off -o EMIF_COM_map.ncd EMIF_COM.ngd EMIF_COM.pcf 
Target Device  : xc2s200
Target Package : pq208
Target Speed   : -5
Mapper Version : spartan2 -- $Revision: 1.36 $
Mapped Date    : Fri Mar 27 16:58:44 2009

Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary
--------------

Design Summary:
Number of errors:      0
Number of warnings:   32
Logic Utilization:
  Number of Slice Latches:          272 out of  4,704    5%
  Number of 4 input LUTs:           166 out of  4,704    3%
Logic Distribution:
    Number of occupied Slices:                         214 out of  2,352    9%
    Number of Slices containing only related logic:    214 out of    214  100%
    Number of Slices containing unrelated logic:         0 out of    214    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs:          181 out of  4,704    3%
      Number used as logic:                       166
      Number used as a route-thru:                 15
   Number of bonded IOBs:            25 out of    140   17%
   Number of GCLKIOBs:                1 out of      4   25%

Total equivalent gate count for design:  2,779
Additional JTAG gate count for IOBs:  1,248
Peak Memory Usage:  143 MB
Total REAL time to MAP completion:  7 secs 
Total CPU time to MAP completion:   5 secs 

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Mapping completed.
See MAP report file "EMIF_COM_map.mrp" for details.