emif_com.v

来自「实现FPGA与DSP之间通信的接口,利用DSP的标准EMIF接口」· Verilog 代码 · 共 69 行

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    15:15:34 03/24/2009 
// Design Name: 
// Module Name:    EMIF_COM 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: CHECK THE FUNCTION OF COMMUNICATION BETWEEN DSP AND FPGA
//					 THROUGH EMIF INTERFACE
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module EMIF_COM(ARE, AOE, AWE, CE2, EXT_INT, CLKOUT2, TEA, TED, LED_OUT, RST);
    input ARE;
    input AOE;
    input AWE;
    input CE2;
    output [3:0] EXT_INT;
    input CLKOUT2;
    input [3:0] TEA;
    inout [15:0] TED;
    output [7:0] LED_OUT;
	 input RST;
	 reg [15:0] DOUT;

	 assign TED = (AOE==1'B0 && ARE==1'B0)?DOUT:16'hZZZZ;
	 
	 reg [15:0] MEMORY[15:0];
	 
	 always @(RST or ARE or AWE or CE2)
	 begin
		if(!RST) 
		begin
			DOUT = 16'D0;
			MEMORY[0] = 16'D0;
			MEMORY[1] = 16'D0;
			MEMORY[2] = 16'D0;
			MEMORY[3] = 16'D0;
			MEMORY[4] = 16'D0;
			MEMORY[5] = 16'D0;
			MEMORY[6] = 16'D0;
			MEMORY[7] = 16'D0;
			MEMORY[8] = 16'D0;
			MEMORY[9] = 16'D0;
			MEMORY[10] = 16'D0;
			MEMORY[11] = 16'D0;
			MEMORY[12] = 16'D0;
			MEMORY[13] = 16'D0;
			MEMORY[14] = 16'D0;
			MEMORY[15] = 16'D0;
		end
		else
		begin
			if(AWE==1'B0 && CE2==1'B0) MEMORY[TEA] = TED+1'B1;
			else
				if(ARE==1'B0 && CE2==1'B0) DOUT = MEMORY[TEA];
		end
	 end
		
endmodule