emif_com.par

实现FPGA与DSP之间通信的接口,利用DSP的标准EMIF接口

Release 9.1i par J.30
Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.

SMARTHC::  Fri Mar 27 16:58:57 2009

par -w -intstyle ise -ol std -t 1 EMIF_COM_map.ncd EMIF_COM.ncd EMIF_COM.pcf 


Constraints file: EMIF_COM.pcf.
Loading device for application Rf_Device from file 'v200.nph' in environment D:\EDA\Xilinx91i.
   "EMIF_COM" is an NCD, version 3.1, device xc2s200, package pq208, speed -5

Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius)
Initializing voltage to 2.375 Volts. (default - Range: 2.375 to 2.625 Volts)

INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
   -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
   internal clocks in this design. The PAR timing summary will list the performance achieved for each clock. Note: For
   the fastest runtime, set the effort level to "std".  For best performance, set the effort level to "high". For a
   balance between the fastest runtime and best performance, set the effort level to "med".

Device speed data version:  "PRODUCTION 1.27 2006-10-19".


Device Utilization Summary:

   Number of External GCLKIOBs               1 out of 4      25%
      Number of LOCed GCLKIOBs               1 out of 1     100%

   Number of External IOBs                  25 out of 140    17%
      Number of LOCed IOBs                  25 out of 25    100%

   Number of SLICEs                        214 out of 2352    9%


Overall effort level (-ol):   Standard 
Placer effort level (-pl):    High 
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard 

WARNING:Par:288 - The signal CLKOUT2_IBUF has no load.  PAR will not attempt to route this signal.

Starting Placer

Phase 1.1
Phase 1.1 (Checksum:989a6c) REAL time: 6 secs 

Phase 2.7
Phase 2.7 (Checksum:1312cfe) REAL time: 6 secs 

Phase 3.31
Phase 3.31 (Checksum:1c9c37d) REAL time: 6 secs 

Phase 4.23
Phase 4.23 (Checksum:26259fc) REAL time: 6 secs 

Phase 5.3
Phase 5.3 (Checksum:2faf07b) REAL time: 6 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 6 secs 

Phase 7.8
........
.....
........
.....
.....
Phase 7.8 (Checksum:d7bb70) REAL time: 6 secs 

Phase 8.5
Phase 8.5 (Checksum:4c4b3f8) REAL time: 6 secs 

Phase 9.18
Phase 9.18 (Checksum:55d4a77) REAL time: 10 secs 

Phase 10.5
Phase 10.5 (Checksum:5f5e0f6) REAL time: 10 secs 

REAL time consumed by placer: 10 secs 
CPU  time consumed by placer: 9 secs 
Writing design to file EMIF_COM.ncd


Total REAL time to Placer completion: 11 secs 
Total CPU time to Placer completion: 9 secs 

Starting Router

Phase 1: 1207 unrouted;       REAL time: 12 secs 

Phase 2: 1207 unrouted;       REAL time: 13 secs 

Phase 3: 268 unrouted;       REAL time: 17 secs 

Phase 4: 268 unrouted; (0)      REAL time: 17 secs 

Phase 5: 268 unrouted; (0)      REAL time: 17 secs 

Phase 6: 0 unrouted; (0)      REAL time: 23 secs 

Phase 7: 0 unrouted; (0)      REAL time: 24 secs 

Phase 8: 0 unrouted; (0)      REAL time: 24 secs 

Total REAL time to Router completion: 24 secs 
Total CPU time to Router completion: 20 secs 

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|un1_MEMORY_15_2_4_0_ |              |      |      |            |             |
|                  a2 |         Local|      |    9 |  0.384     |  3.664      |
+---------------------+--------------+------+------+------------+-------------+
|         MEMORY_15_3 |         Local|      |    8 |  0.510     |  3.860      |
+---------------------+--------------+------+------+------------+-------------+
|     un1_TEA_12_0_a2 |         Local|      |    8 |  2.550     |  3.706      |
+---------------------+--------------+------+------+------------+-------------+
|     un1_TEA_13_0_a2 |         Local|      |    8 |  1.953     |  3.523      |
+---------------------+--------------+------+------+------------+-------------+
|     un1_TEA_21_0_a2 |         Local|      |    8 |  1.454     |  2.485      |
+---------------------+--------------+------+------+------------+-------------+
|     un1_TEA_14_0_a2 |         Local|      |    8 |  2.449     |  3.592      |
+---------------------+--------------+------+------+------------+-------------+
|     un1_TEA_22_0_a2 |         Local|      |    8 |  2.488     |  3.700      |
+---------------------+--------------+------+------+------------+-------------+
|     un1_TEA_15_0_a2 |         Local|      |    8 |  1.998     |  3.484      |
+---------------------+--------------+------+------+------------+-------------+
|     un1_TEA_23_0_a2 |         Local|      |    8 |  2.350     |  3.931      |
+---------------------+--------------+------+------+------------+-------------+
|     un1_TEA_16_0_a2 |         Local|      |    8 |  1.890     |  3.518      |
+---------------------+--------------+------+------+------------+-------------+
|     un1_TEA_24_0_a2 |         Local|      |    8 |  1.524     |  3.230      |
+---------------------+--------------+------+------+------------+-------------+
|     un1_TEA_17_0_a2 |         Local|      |    8 |  0.161     |  3.700      |
+---------------------+--------------+------+------+------------+-------------+
|     un1_TEA_25_0_a2 |         Local|      |    8 |  0.375     |  3.684      |
+---------------------+--------------+------+------+------------+-------------+
|     un1_TEA_18_0_a2 |         Local|      |    8 |  2.256     |  3.603      |
+---------------------+--------------+------+------+------------+-------------+
|     un1_TEA_26_0_a2 |         Local|      |    8 |  2.244     |  3.575      |
+---------------------+--------------+------+------+------------+-------------+
|     un1_TEA_19_0_a2 |         Local|      |    8 |  0.241     |  3.691      |
+---------------------+--------------+------+------+------------+-------------+
|     un1_TEA_20_0_a2 |         Local|      |    8 |  2.114     |  3.824      |
+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.


   The Delay Summary Report


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        2.603
   The MAXIMUM PIN DELAY IS:                               8.490
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   4.791

   Listing Pin Delays by value: (nsec)

    d < 2.00   < d < 4.00  < d < 6.00  < d < 8.00  < d < 9.00  d >= 9.00
   ---------   ---------   ---------   ---------   ---------   ---------
         499         515         126          65           2           0

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

------------------------------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic  | Absolute   |Number of
                                            |            |            | Levels | Slack      |errors   
------------------------------------------------------------------------------------------------------


All constraints were met.


Generating Pad Report.

All signals are completely routed.

WARNING:Par:283 - There are 1 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.

Total REAL time to PAR completion: 25 secs 
Total CPU time to PAR completion: 21 secs 

Peak Memory Usage:  128 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 3
Number of info messages: 1

Writing design to file EMIF_COM.ncd



PAR done!