emif_com.unroutes

实现FPGA与DSP之间通信的接口,利用DSP的标准EMIF接口

Release 9.1i - par J.30
Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.

Fri Mar 27 16:59:23 2009

All signals are completely routed.

WARNING:ParHelpers:361 - There are 1 loadless signals in this design. This design will cause Bitgen to issue DRC
   warnings.

   CLKOUT2_IBUF