emif_com.edn

实现FPGA与DSP之间通信的接口,利用DSP的标准EMIF接口

(edif (rename emif_com "EMIF_COM")
  (edifVersion 2 0 0)
  (edifLevel 0)
  (keywordMap (keywordLevel 0))
  (status
    (written
      (timeStamp 2009 3 27 16 35 42)
      (author "Synplicity, Inc.")
      (program "Synplify Pro" (version "8.1.0, Build 540R"))
     )
   )
  (library VIRTEX
    (edifLevel 0)
    (technology (numberDefinition ))
    (cell IBUF (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port O (direction OUTPUT))
           (port I (direction INPUT))
         )
       )
    )
    (cell IOBUF (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port O (direction OUTPUT))
           (port IO (direction INOUT))
           (port I (direction INPUT))
           (port T (direction INPUT))
         )
       )
    )
    (cell OBUFT (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port O (direction OUTPUT))
           (port I (direction INPUT))
           (port T (direction INPUT))
         )
       )
    )
    (cell LUT4 (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I0 (direction INPUT))
           (port I1 (direction INPUT))
           (port I2 (direction INPUT))
           (port I3 (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
    (cell LUT3 (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I0 (direction INPUT))
           (port I1 (direction INPUT))
           (port I2 (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
    (cell LUT2 (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I0 (direction INPUT))
           (port I1 (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
    (cell LUT1 (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I0 (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
    (cell XORCY (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port LI (direction INPUT))
           (port CI (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
    (cell MUXCY_L (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port DI (direction INPUT))
           (port CI (direction INPUT))
           (port S (direction INPUT))
           (port LO (direction OUTPUT))
         )
       )
    )
    (cell MUXF6 (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I0 (direction INPUT))
           (port I1 (direction INPUT))
           (port S (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
    (cell MUXF5 (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I0 (direction INPUT))
           (port I1 (direction INPUT))
           (port S (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
    (cell BUF (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
  )
  (library UNILIB
    (edifLevel 0)
    (technology (numberDefinition ))
    (cell LDC (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port Q (direction OUTPUT))
           (port D (direction INPUT))
           (port G (direction INPUT)
 )
           (port CLR (direction INPUT))
         )
       )
    )
    (cell INV (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
    (cell GND (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port G (direction OUTPUT))
         )
       )
    )
    (cell VCC (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port P (direction OUTPUT))
         )
       )
    )
  )
  (library work
    (edifLevel 0)
    (technology (numberDefinition ))
    (cell (rename emif_com "EMIF_COM") (cellType GENERIC)
       (view verilog (viewType NETLIST)
         (interface
           (port (array (rename ext_int "EXT_INT[3:0]") 4) (direction OUTPUT))
           (port (array (rename tea "TEA[3:0]") 4) (direction INPUT))
           (port (array (rename ted "TED[15:0]") 16) (direction INOUT))
           (port (array (rename led_out "LED_OUT[7:0]") 8) (direction OUTPUT))
           (port ARE (direction INPUT)
 )
           (port AOE (direction INPUT)
 )
           (port AWE (direction INPUT)
 )
           (port CE2 (direction INPUT)
 )
           (port CLKOUT2 (direction INPUT)
 )
           (port RST (direction INPUT)
 )
         )
         (contents
          (instance un48_MEMORY_axb_1 (viewRef PRIM (cellRef LUT1 (libraryRef VIRTEX)))
           (property init (string "2"))
           (property mapinfo (string "FMAP"))
          )
          (instance un48_MEMORY_axb_2 (viewRef PRIM (cellRef LUT1 (libraryRef VIRTEX)))
           (property init (string "2"))
           (property mapinfo (string "FMAP"))
          )
          (instance un48_MEMORY_axb_3 (viewRef PRIM (cellRef LUT1 (libraryRef VIRTEX)))
           (property init (string "2"))
           (property mapinfo (string "FMAP"))
          )
          (instance un48_MEMORY_axb_4 (viewRef PRIM (cellRef LUT1 (libraryRef VIRTEX)))
           (property init (string "2"))
           (property mapinfo (string "FMAP"))
          )
          (instance un48_MEMORY_axb_5 (viewRef PRIM (cellRef LUT1 (libraryRef VIRTEX)))
           (property init (string "2"))
           (property mapinfo (string "FMAP"))
          )
          (instance un48_MEMORY_axb_6 (viewRef PRIM (cellRef LUT1 (libraryRef VIRTEX)))
           (property init (string "2"))
           (property mapinfo (string "FMAP"))
          )
          (instance un48_MEMORY_axb_7 (viewRef PRIM (cellRef LUT1 (libraryRef VIRTEX)))
           (property init (string "2"))
           (property mapinfo (string "FMAP"))
          )
          (instance un48_MEMORY_axb_8 (viewRef PRIM (cellRef LUT1 (libraryRef VIRTEX)))
           (property init (string "2"))
           (property mapinfo (string "FMAP"))
          )
          (instance un48_MEMORY_axb_9 (viewRef PRIM (cellRef LUT1 (libraryRef VIRTEX)))
           (property init (string "2"))
           (property mapinfo (string "FMAP"))
          )
          (instance un48_MEMORY_axb_10 (viewRef PRIM (cellRef LUT1 (libraryRef VIRTEX)))
           (property init (string "2"))
           (property mapinfo (string "FMAP"))
          )
          (instance un48_MEMORY_axb_11 (viewRef PRIM (cellRef LUT1 (libraryRef VIRTEX)))
           (property init (string "2"))
           (property mapinfo (string "FMAP"))
          )
          (instance un48_MEMORY_axb_12 (viewRef PRIM (cellRef LUT1 (libraryRef VIRTEX)))
           (property init (string "2"))
           (property mapinfo (string "FMAP"))
          )
          (instance un48_MEMORY_axb_13 (viewRef PRIM (cellRef LUT1 (libraryRef VIRTEX)))
           (property init (string "2"))
           (property mapinfo (string "FMAP"))
          )
          (instance un48_MEMORY_axb_14 (viewRef PRIM (cellRef LUT1 (libraryRef VIRTEX)))
           (property init (string "2"))
           (property mapinfo (string "FMAP"))
          )
          (instance (rename TEA_c_1_3 "TEA_c_1[3]") (viewRef PRIM (cellRef BUF (libraryRef VIRTEX)))          )
          (instance (rename TEA_c_0_3 "TEA_c_0[3]") (viewRef PRIM (cellRef BUF (libraryRef VIRTEX)))          )
          (instance (rename DOUT_5 "DOUT[5]") (viewRef PRIM (cellRef LDC (libraryRef UNILIB)))
          )