emif_com.bgn

实现FPGA与DSP之间通信的接口,利用DSP的标准EMIF接口

Release 9.1i - Bitgen J.30
Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.
Loading device for application Rf_Device from file 'v200.nph' in environment
D:\EDA\Xilinx91i.
   "EMIF_COM" is an NCD, version 3.1, device xc2s200, package pq208, speed -5
Opened constraints file EMIF_COM.pcf.

Fri Mar 27 16:59:54 2009

D:\EDA\Xilinx91i\bin\nt\bitgen.exe -intstyle ise -w -g DebugBitstream:No -g Binary:yes -g Gclkdel0:11111 -g Gclkdel1:11111 -g Gclkdel2:11111 -g Gclkdel3:11111 -g ConfigRate:4 -g CclkPin:PullUp -g M0Pin:PullUp -g M1Pin:PullUp -g M2Pin:PullUp -g ProgPin:PullUp -g DonePin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GSR_cycle:6 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g Persist:No -m -g ReadBack -g DonePipe:No -g DriveDone:No EMIF_COM.ncd 

WARNING:Bitgen:151 - Generating a readback bitstream, but the Persist option is
   set to "No" in the configuration bitstream.  Readback will not be possible
   unless the Persist option is set to "Yes".
Summary of Bitgen Options:
+----------------------+----------------------+
| Option Name          | Current Setting      |
+----------------------+----------------------+
| Compress             | (Not Specified)*     |
+----------------------+----------------------+
| Readback             | (Enabled)            |
+----------------------+----------------------+
| DebugBitstream       | No**                 |
+----------------------+----------------------+
| ConfigRate           | 4**                  |
+----------------------+----------------------+
| StartupClk           | Cclk**               |
+----------------------+----------------------+
| CclkPin              | Pullup**             |
+----------------------+----------------------+
| DonePin              | Pullup**             |
+----------------------+----------------------+
| M0Pin                | Pullup**             |
+----------------------+----------------------+
| M1Pin                | Pullup**             |
+----------------------+----------------------+
| M2Pin                | Pullup**             |
+----------------------+----------------------+
| ProgPin              | Pullup**             |
+----------------------+----------------------+
| TckPin               | Pullup**             |
+----------------------+----------------------+
| TdiPin               | Pullup**             |
+----------------------+----------------------+
| TdoPin               | Pullup               |
+----------------------+----------------------+
| TmsPin               | Pullup**             |
+----------------------+----------------------+
| UnusedPin            | Pulldown**           |
+----------------------+----------------------+
| GSR_cycle            | 6**                  |
+----------------------+----------------------+
| GWE_cycle            | 6**                  |
+----------------------+----------------------+
| GTS_cycle            | 5**                  |
+----------------------+----------------------+
| LCK_cycle            | NoWait**             |
+----------------------+----------------------+
| DONE_cycle           | 4**                  |
+----------------------+----------------------+
| Persist              | No**                 |
+----------------------+----------------------+
| DriveDone            | No**                 |
+----------------------+----------------------+
| DonePipe             | No**                 |
+----------------------+----------------------+
| Security             | None**               |
+----------------------+----------------------+
| UserID               | 0xFFFFFFFF**         |
+----------------------+----------------------+
| Gclkdel0             | 11111**              |
+----------------------+----------------------+
| Gclkdel1             | 11111**              |
+----------------------+----------------------+
| Gclkdel2             | 11111**              |
+----------------------+----------------------+
| Gclkdel3             | 11111**              |
+----------------------+----------------------+
| ActiveReconfig       | No*                  |
+----------------------+----------------------+
| ActivateGclk         | No*                  |
+----------------------+----------------------+
| PartialMask0         | (Not Specified)*     |
+----------------------+----------------------+
| PartialMask1         | (Not Specified)*     |
+----------------------+----------------------+
| PartialGclk          | (Not Specified)*     |
+----------------------+----------------------+
| PartialLeft          | (Not Specified)*     |
+----------------------+----------------------+
| PartialRight         | (Not Specified)*     |
+----------------------+----------------------+
| IEEE1532             | No*                  |
+----------------------+----------------------+
| Binary               | Yes                  |
+----------------------+----------------------+
 *  Default setting.
 ** The specified setting matches the default setting.

Running DRC.
WARNING:PhysDesignRules:372 - Gated clock. Clock net un1_MEMORY_15_2_4_0_a2 is
   sourced by a combinatorial pin. This is not good design practice. Use the CE
   pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net MEMORY_15_3 is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net un1_TEA_12_0_a2 is sourced
   by a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net un1_TEA_13_0_a2 is sourced
   by a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net un1_TEA_21_0_a2 is sourced
   by a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net un1_TEA_14_0_a2 is sourced
   by a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net un1_TEA_22_0_a2 is sourced
   by a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net un1_TEA_15_0_a2 is sourced
   by a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net un1_TEA_23_0_a2 is sourced
   by a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net un1_TEA_16_0_a2 is sourced
   by a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net un1_TEA_24_0_a2 is sourced
   by a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net un1_TEA_17_0_a2 is sourced
   by a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net un1_TEA_25_0_a2 is sourced
   by a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net un1_TEA_18_0_a2 is sourced
   by a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net un1_TEA_26_0_a2 is sourced
   by a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net un1_TEA_19_0_a2 is sourced
   by a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net un1_TEA_20_0_a2 is sourced
   by a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:367 - The signal <CLKOUT2_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
DRC detected 0 errors and 18 warnings.
Creating bit map...
Saving bit stream in "emif_com.bit".
Saving bit stream in "emif_com.bin".
Saving Readback bit file emif_com.rbb.
Creating bit mask...
Saving mask bit stream in "emif_com.msk".
Bitstream generation is complete.