emif_com.tlg

实现FPGA与DSP之间通信的接口,利用DSP的标准EMIF接口

Selecting top level module EMIF_COM
@N:"E:\ISE_Prj\EMIF_COM\EMIF_COM.v":21:7:21:14|Synthesizing module EMIF_COM

@W: CG296 :"E:\ISE_Prj\EMIF_COM\EMIF_COM.v":38:11:38:35|Incomplete sensitivity list - assuming completeness
@W: CG290 :"E:\ISE_Prj\EMIF_COM\EMIF_COM.v":62:37:62:39|Referenced variable TEA is not in sensitivity list
@W: CG290 :"E:\ISE_Prj\EMIF_COM\EMIF_COM.v":62:44:62:46|Referenced variable TED is not in sensitivity list
@W: CL118 :"E:\ISE_Prj\EMIF_COM\EMIF_COM.v":40:2:40:3|Latch generated from always block for signal MEMORY_15_[15:0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"E:\ISE_Prj\EMIF_COM\EMIF_COM.v":40:2:40:3|Latch generated from always block for signal MEMORY_14_[15:0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"E:\ISE_Prj\EMIF_COM\EMIF_COM.v":40:2:40:3|Latch generated from always block for signal MEMORY_13_[15:0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"E:\ISE_Prj\EMIF_COM\EMIF_COM.v":40:2:40:3|Latch generated from always block for signal MEMORY_12_[15:0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"E:\ISE_Prj\EMIF_COM\EMIF_COM.v":40:2:40:3|Latch generated from always block for signal MEMORY_11_[15:0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"E:\ISE_Prj\EMIF_COM\EMIF_COM.v":40:2:40:3|Latch generated from always block for signal MEMORY_10_[15:0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"E:\ISE_Prj\EMIF_COM\EMIF_COM.v":40:2:40:3|Latch generated from always block for signal MEMORY_9_[15:0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"E:\ISE_Prj\EMIF_COM\EMIF_COM.v":40:2:40:3|Latch generated from always block for signal MEMORY_8_[15:0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"E:\ISE_Prj\EMIF_COM\EMIF_COM.v":40:2:40:3|Latch generated from always block for signal MEMORY_7_[15:0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"E:\ISE_Prj\EMIF_COM\EMIF_COM.v":40:2:40:3|Latch generated from always block for signal MEMORY_6_[15:0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"E:\ISE_Prj\EMIF_COM\EMIF_COM.v":40:2:40:3|Latch generated from always block for signal MEMORY_5_[15:0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"E:\ISE_Prj\EMIF_COM\EMIF_COM.v":40:2:40:3|Latch generated from always block for signal MEMORY_4_[15:0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"E:\ISE_Prj\EMIF_COM\EMIF_COM.v":40:2:40:3|Latch generated from always block for signal MEMORY_3_[15:0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"E:\ISE_Prj\EMIF_COM\EMIF_COM.v":40:2:40:3|Latch generated from always block for signal MEMORY_2_[15:0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"E:\ISE_Prj\EMIF_COM\EMIF_COM.v":40:2:40:3|Latch generated from always block for signal MEMORY_1_[15:0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"E:\ISE_Prj\EMIF_COM\EMIF_COM.v":40:2:40:3|Latch generated from always block for signal MEMORY_0_[15:0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"E:\ISE_Prj\EMIF_COM\EMIF_COM.v":40:2:40:3|Latch generated from always block for signal DOUT[15:0], probably caused by a missing assignment in an if or case stmt
@W: CL157 :"E:\ISE_Prj\EMIF_COM\EMIF_COM.v":26:17:26:23|*Output EXT_INT has undriven bits - a simulation mismatch is possible 
@W: CL157 :"E:\ISE_Prj\EMIF_COM\EMIF_COM.v":30:17:30:23|*Output LED_OUT has undriven bits - a simulation mismatch is possible 
@W: CL159 :"E:\ISE_Prj\EMIF_COM\EMIF_COM.v":27:10:27:16|Input CLKOUT2 is unused