timing.twr

来自「实现FPGA与DSP之间通信的接口,利用DSP的标准EMIF接口」· TWR 代码 · 共 16 行

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

------------------------------------------------------------------------------------------------------
  Constraint                                |  Check  | Worst Case |  Best Case | Timing |   Timing   
                                            |         |    Slack   | Achievable | Errors |    Score   
------------------------------------------------------------------------------------------------------
* TS_CLKOUT2 = PERIOD TIMEGRP "CLKOUT2" 6.5 | SETUP   |    -0.245ns|     6.750ns|       1|         245
  05 ns HIGH 50%                            | HOLD    |     3.430ns|            |       0|           0
------------------------------------------------------------------------------------------------------


1 constraint not met.