emif_com.srr

实现FPGA与DSP之间通信的接口,利用DSP的标准EMIF接口

#Program: Synplify Pro 8.1
#OS: Windows_NT

$ Start of Compile
#Fri Mar 27 16:35:33 2009

Synplicity Verilog Compiler, version 3.1.0, Build 049R, built May  3 2005
Copyright (C) 1994-2005, Synplicity Inc.  All Rights Reserved

@I::"d:\EDA\Synplicity\fpga_81\lib\xilinx\unisim.v"
@I::"d:\EDA\Synplicity\fpga_81\bin\..\lib\xilinx\unisim.v"
@I::"E:\ISE_Prj\EMIF_COM\EMIF_COM.v"
Verilog syntax check successful!
File E:\ISE_Prj\EMIF_COM\EMIF_COM.v changed - recompiling
Selecting top level module EMIF_COM
@N:"E:\ISE_Prj\EMIF_COM\EMIF_COM.v":21:7:21:14|Synthesizing module EMIF_COM

@W: CG296 :"E:\ISE_Prj\EMIF_COM\EMIF_COM.v":38:11:38:35|Incomplete sensitivity list - assuming completeness
@W: CG290 :"E:\ISE_Prj\EMIF_COM\EMIF_COM.v":62:37:62:39|Referenced variable TEA is not in sensitivity list
@W: CG290 :"E:\ISE_Prj\EMIF_COM\EMIF_COM.v":62:44:62:46|Referenced variable TED is not in sensitivity list
@W: CL118 :"E:\ISE_Prj\EMIF_COM\EMIF_COM.v":40:2:40:3|Latch generated from always block for signal MEMORY_15_[15:0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"E:\ISE_Prj\EMIF_COM\EMIF_COM.v":40:2:40:3|Latch generated from always block for signal MEMORY_14_[15:0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"E:\ISE_Prj\EMIF_COM\EMIF_COM.v":40:2:40:3|Latch generated from always block for signal MEMORY_13_[15:0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"E:\ISE_Prj\EMIF_COM\EMIF_COM.v":40:2:40:3|Latch generated from always block for signal MEMORY_12_[15:0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"E:\ISE_Prj\EMIF_COM\EMIF_COM.v":40:2:40:3|Latch generated from always block for signal MEMORY_11_[15:0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"E:\ISE_Prj\EMIF_COM\EMIF_COM.v":40:2:40:3|Latch generated from always block for signal MEMORY_10_[15:0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"E:\ISE_Prj\EMIF_COM\EMIF_COM.v":40:2:40:3|Latch generated from always block for signal MEMORY_9_[15:0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"E:\ISE_Prj\EMIF_COM\EMIF_COM.v":40:2:40:3|Latch generated from always block for signal MEMORY_8_[15:0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"E:\ISE_Prj\EMIF_COM\EMIF_COM.v":40:2:40:3|Latch generated from always block for signal MEMORY_7_[15:0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"E:\ISE_Prj\EMIF_COM\EMIF_COM.v":40:2:40:3|Latch generated from always block for signal MEMORY_6_[15:0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"E:\ISE_Prj\EMIF_COM\EMIF_COM.v":40:2:40:3|Latch generated from always block for signal MEMORY_5_[15:0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"E:\ISE_Prj\EMIF_COM\EMIF_COM.v":40:2:40:3|Latch generated from always block for signal MEMORY_4_[15:0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"E:\ISE_Prj\EMIF_COM\EMIF_COM.v":40:2:40:3|Latch generated from always block for signal MEMORY_3_[15:0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"E:\ISE_Prj\EMIF_COM\EMIF_COM.v":40:2:40:3|Latch generated from always block for signal MEMORY_2_[15:0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"E:\ISE_Prj\EMIF_COM\EMIF_COM.v":40:2:40:3|Latch generated from always block for signal MEMORY_1_[15:0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"E:\ISE_Prj\EMIF_COM\EMIF_COM.v":40:2:40:3|Latch generated from always block for signal MEMORY_0_[15:0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"E:\ISE_Prj\EMIF_COM\EMIF_COM.v":40:2:40:3|Latch generated from always block for signal DOUT[15:0], probably caused by a missing assignment in an if or case stmt
@W: CL157 :"E:\ISE_Prj\EMIF_COM\EMIF_COM.v":26:17:26:23|*Output EXT_INT has undriven bits - a simulation mismatch is possible 
@W: CL157 :"E:\ISE_Prj\EMIF_COM\EMIF_COM.v":30:17:30:23|*Output LED_OUT has undriven bits - a simulation mismatch is possible 
@W: CL159 :"E:\ISE_Prj\EMIF_COM\EMIF_COM.v":27:10:27:16|Input CLKOUT2 is unused
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Mar 27 16:35:36 2009

###########################################################[
Version 8.1
Synplicity Xilinx Technology Mapper, Version 8.1.0, Build 540R, Built May  9 2005
Copyright (C) 1994-2005, Synplicity Inc.  All Rights Reserved
Reading constraint file: E:\ISE_Prj\EMIF_COM\EMIF_COM.sdc
Reading Xilinx I/O pad type table from file <d:\EDA\Synplicity\fpga_81\lib/xilinx/x_io_tbl.txt> 
Reading Xilinx Rocket I/O parameter type table from file <d:\EDA\Synplicity\fpga_81\lib/xilinx/gttype.txt> 


@W: MO111 :"e:\ise_prj\emif_com\emif_com.v":30:17:30:23|tristate driver LED_OUT_8 on net LED_OUT_8 has its enable tied to GND (module EMIF_COM) 
@W: MO111 :"e:\ise_prj\emif_com\emif_com.v":30:17:30:23|tristate driver LED_OUT_7 on net LED_OUT_7 has its enable tied to GND (module EMIF_COM) 
@W: MO111 :"e:\ise_prj\emif_com\emif_com.v":30:17:30:23|tristate driver LED_OUT_6 on net LED_OUT_6 has its enable tied to GND (module EMIF_COM) 
@W: MO111 :"e:\ise_prj\emif_com\emif_com.v":30:17:30:23|tristate driver LED_OUT_5 on net LED_OUT_5 has its enable tied to GND (module EMIF_COM) 
@W: MO111 :"e:\ise_prj\emif_com\emif_com.v":30:17:30:23|tristate driver LED_OUT_4 on net LED_OUT_4 has its enable tied to GND (module EMIF_COM) 
@W: MO111 :"e:\ise_prj\emif_com\emif_com.v":30:17:30:23|tristate driver LED_OUT_3 on net LED_OUT_3 has its enable tied to GND (module EMIF_COM) 
@W: MO111 :"e:\ise_prj\emif_com\emif_com.v":30:17:30:23|tristate driver LED_OUT_2 on net LED_OUT_2 has its enable tied to GND (module EMIF_COM) 
@W: MO111 :"e:\ise_prj\emif_com\emif_com.v":30:17:30:23|tristate driver LED_OUT_1 on net LED_OUT_1 has its enable tied to GND (module EMIF_COM) 
@W: MO111 :"e:\ise_prj\emif_com\emif_com.v":26:17:26:23|tristate driver EXT_INT_4 on net EXT_INT_4 has its enable tied to GND (module EMIF_COM) 
@W: MO111 :"e:\ise_prj\emif_com\emif_com.v":26:17:26:23|tristate driver EXT_INT_3 on net EXT_INT_3 has its enable tied to GND (module EMIF_COM) 
@W: MO111 :"e:\ise_prj\emif_com\emif_com.v":26:17:26:23|tristate driver EXT_INT_2 on net EXT_INT_2 has its enable tied to GND (module EMIF_COM) 
@W: MO111 :"e:\ise_prj\emif_com\emif_com.v":26:17:26:23|tristate driver EXT_INT_1 on net EXT_INT_1 has its enable tied to GND (module EMIF_COM) 
@N: MT204 |Autoconstrain Mode is ON
@N|Only System clock will be Autoconstrained
RTL optimization done.
Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:0m:2s		    -2.64ns		 182 /         0
   2		0h:0m:2s		    -2.64ns		 182 /         0
   3		0h:0m:2s		    -2.64ns		 182 /         0
------------------------------------------------------------

Timing driven replication report
No replication required.

Timing driven replication report
No replication required.

Timing driven replication report
No replication required.

Timing driven replication report
No replication required.

Timing driven replication report
No replication required.

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:0m:3s		    -2.27ns		 182 /         0
   2		0h:0m:3s		    -2.27ns		 182 /         0
   3		0h:0m:3s		    -2.27ns		 182 /         0
Timing driven replication report
No replication required.

   4		0h:0m:3s		    -2.27ns		 182 /         0
   5		0h:0m:3s		    -2.27ns		 182 /         0
   6		0h:0m:3s		    -2.27ns		 182 /         0
------------------------------------------------------------

Timing driven replication report
No replication required.

Timing driven replication report
No replication required.

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:0m:3s		    -2.27ns		 182 /         0
   2		0h:0m:3s		    -2.27ns		 182 /         0
   3		0h:0m:3s		    -2.27ns		 182 /         0
Timing driven replication report
No replication required.

   4		0h:0m:3s		    -2.27ns		 182 /         0
   5		0h:0m:3s		    -2.27ns		 182 /         0
   6		0h:0m:3s		    -2.27ns		 182 /         0
------------------------------------------------------------

Net buffering Report for view:work.EMIF_COM(verilog):
@N: FX104 |Net "TEA_c[3]" with "144" loads has been buffered by "2" buffers due to a soft fanout limit of "100" 
Added 2 Buffers
Added 0 Registers via replication
Added 0 LUTs via replication

@N: FX164 |The option to pack flops in the IOB has not been specified 
Writing Analyst data base E:\ISE_Prj\EMIF_COM\EMIF_COM.srm
Writing EDIF Netlist and constraint files
@W:"e:\ise_prj\emif_com\emif_com.v":62:6:64:29|Net MEMORY_15_3 appears to be a clock source which was not identified. Assuming default frequency. 
@W:"e:\ise_prj\emif_com\emif_com.v":40:2:40:3|Net un1_MEMORY_15_2_4_0_a2 appears to be a clock source which was not identified. Assuming default frequency. 
@W:"e:\ise_prj\emif_com\emif_com.v":40:2:40:3|Net un1_TEA_26_0_a2 appears to be a clock source which was not identified. Assuming default frequency. 
@W:"e:\ise_prj\emif_com\emif_com.v":40:2:40:3|Net un1_TEA_25_0_a2 appears to be a clock source which was not identified. Assuming default frequency. 
@W:"e:\ise_prj\emif_com\emif_com.v":40:2:40:3|Net un1_TEA_24_0_a2 appears to be a clock source which was not identified. Assuming default frequency. 
@W:"e:\ise_prj\emif_com\emif_com.v":40:2:40:3|Net un1_TEA_23_0_a2 appears to be a clock source which was not identified. Assuming default frequency. 
@W:"e:\ise_prj\emif_com\emif_com.v":40:2:40:3|Net un1_TEA_22_0_a2 appears to be a clock source which was not identified. Assuming default frequency. 
@W:"e:\ise_prj\emif_com\emif_com.v":40:2:40:3|Net un1_TEA_21_0_a2 appears to be a clock source which was not identified. Assuming default frequency. 
@W:"e:\ise_prj\emif_com\emif_com.v":40:2:40:3|Net un1_TEA_20_0_a2 appears to be a clock source which was not identified. Assuming default frequency. 
@W:"e:\ise_prj\emif_com\emif_com.v":40:2:40:3|Net un1_TEA_19_0_a2 appears to be a clock source which was not identified. Assuming default frequency. 
@W:"e:\ise_prj\emif_com\emif_com.v":40:2:40:3|Net un1_TEA_18_0_a2 appears to be a clock source which was not identified. Assuming default frequency. 
@W:"e:\ise_prj\emif_com\emif_com.v":40:2:40:3|Net un1_TEA_17_0_a2 appears to be a clock source which was not identified. Assuming default frequency. 
@W:"e:\ise_prj\emif_com\emif_com.v":40:2:40:3|Net un1_TEA_16_0_a2 appears to be a clock source which was not identified. Assuming default frequency. 
@W:"e:\ise_prj\emif_com\emif_com.v":40:2:40:3|Net un1_TEA_15_0_a2 appears to be a clock source which was not identified. Assuming default frequency. 
@W:"e:\ise_prj\emif_com\emif_com.v":40:2:40:3|Net un1_TEA_14_0_a2 appears to be a clock source which was not identified. Assuming default frequency. 
@W:"e:\ise_prj\emif_com\emif_com.v":40:2:40:3|Net un1_TEA_13_0_a2 appears to be a clock source which was not identified. Assuming default frequency. 
@W:"e:\ise_prj\emif_com\emif_com.v":40:2:40:3|Net un1_TEA_12_0_a2 appears to be a clock source which was not identified. Assuming default frequency. 


##### START OF TIMING REPORT #####[
# Timing Report written on Fri Mar 27 16:35:42 2009
#


Top view:               EMIF_COM
Requested Frequency:    155.7 MHz
Wire load mode:         top
Paths requested:        0
Constraint File(s):    E:\ISE_Prj\EMIF_COM\EMIF_COM.sdc
                       
@N: MT195 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..

@N: MT197 |Clock constraints cover only FF-to-FF paths associated with the clock..



Performance Summary 
*******************


Worst slack in design: -1.898

                   Requested     Estimated     Requested     Estimated                Clock      Clock           
Starting Clock     Frequency     Frequency     Period        Period        Slack      Type       Group           
-----------------------------------------------------------------------------------------------------------------
System             155.7 MHz     120.2 MHz     6.422         8.320         -1.898     system     default_clkgroup
=================================================================================================================





Interface Information 
*********************

		No IO constraint found 


##### END OF TIMING REPORT #####]

---------------------------------------
Resource Usage Report for EMIF_COM 

Mapping to part: xc2s200pq208-5
Cell usage:
BUF             2 uses
GND             1 use
LDC             272 uses
MUXCY_L         14 uses
MUXF5           64 uses
MUXF6           32 uses
VCC             1 use
XORCY           15 uses
LUT1            15 uses
LUT2            1 use
LUT3            147 uses
LUT4            16 uses

I/O primitives: 37
IBUF           9 uses
IOBUF          16 uses
OBUFT          12 uses

I/O Register bits:                  0
Register bits not including I/Os:   0 (0%)

Mapping Summary:
Total  LUTs: 179 (3%)

Mapper successful!
Process took 0h:0m:5s realtime, 0h:0m:5s cputime
###########################################################]