traplog.tlg

实现FPGA与DSP之间通信的接口,利用DSP的标准EMIF接口

@N:".\gentmp0a02432":4:7:4:9|Synthesizing work.top.gen 
@N:"syng0a02432":16:7:16:12|Synthesizing work.ram_rw.select_ram 
@N:"d:\EDA\Synplicity\fpga_81\lib\xilinx\unisim.vhd":15912:10:15912:17|Synthesizing unisim.ram16x1s.syn_black_box 
Post processing for unisim.ram16x1s.syn_black_box
@W:"syng0a02432":1091:7:1091:12|Signal out_en is undriven 
@W:"syng0a02432":1093:7:1093:12|Signal wrt_en is undriven 
Post processing for work.ram_rw.select_ram
@W: CL159 :"syng0a02432":32:8:32:11|Input oclk is unused
Post processing for work.top.gen