emif_com.ncf

实现FPGA与DSP之间通信的接口,利用DSP的标准EMIF接口

#
# Constraints generated by Synplify Pro 8.1.0, Build 540R
#

# Period Constraints

#Begin clock constraints
#End clock constraints

# Output Constraints
# Input Constraints

# I/O Registers Packing Constraints
INST "DOUT[4]" IOB=FALSE;
INST "DOUT[3]" IOB=FALSE;
INST "DOUT[2]" IOB=FALSE;
INST "DOUT[1]" IOB=FALSE;
INST "DOUT[0]" IOB=FALSE;
INST "DOUT[15]" IOB=FALSE;
INST "DOUT[14]" IOB=FALSE;
INST "DOUT[13]" IOB=FALSE;
INST "DOUT[12]" IOB=FALSE;
INST "DOUT[11]" IOB=FALSE;
INST "DOUT[10]" IOB=FALSE;
INST "DOUT[9]" IOB=FALSE;
INST "DOUT[8]" IOB=FALSE;
INST "DOUT[7]" IOB=FALSE;
INST "DOUT[6]" IOB=FALSE;
INST "DOUT[5]" IOB=FALSE;

# Location Constraints

# End of generated constraints