emif_com.plg

来自「实现FPGA与DSP之间通信的接口,利用DSP的标准EMIF接口」· PLG 代码 · 共 12 行

@P:  Worst Slack : -1.898
@P:  System - Estimated Frequency : 120.2 MHz
@P:  System - Requested Frequency : 155.7 MHz
@P:  System - Estimated Period : 8.320
@P:  System - Requested Period : 6.422
@P:  System - Slack : -1.898
@P: EMIF_COM Part : xc2s200pq208-5
@P: EMIF_COM I/O primitives : 37
@P: EMIF_COM I/O Register bits : 0
@P: EMIF_COM Register bits (Non I/O) : 0 (0%)
@P: EMIF_COM Total Luts : 179 (3%)